To display this email in a browser, please click here
Header


  May 2010 Issue

   
In this issue
 

Welcome to the May issue of eEuronews!

CDNLive! EMEA was a great success. More than 550 participants from more than 130 companies and universities attended the conference.

During the keynotes, our customers had the opportunity to hear about our new EDA360 vision and the newly launched Open Integration Platform. This year's guest speakers were Subramani Kengeri, Vice President Design Solutions, Globalfoundries, and Dr. Alberto Sangiovanni-Vincentelli, Professor UC Berkeley and Co-Founder of Cadence. If you did not have the time to attend the keynotes you can listen to them here.

We have received lots of positive feedback from our customers. You can listen to some of the feedback here and get an impression of this year's event.

As always, the networking opportunities at the conference are a very important factor of the event and attendees appreciated having a forum to learn how others approach technology issues and to get new ideas for their work.

As every year, we want to acknowledge all the speakers that took their time to prepare and deliver excellent presentations. Attendees were encouraged to vote for the best papers in each major design category. Congratulations to the winners listed here. Presentations from the conference will be available on the CDNLive! web site in the coming days.

This is only a snapshot of all the activities that took place over the three days. It was a very exciting event so I encourage you to watch the videos to get your own impression.

Best regards
Wolfgang Stronski
EMEA Marketing Director

p.s. the next CDNLive! in our region will take place in Israel on October 18th.


In the news  
Custom Design  
Functional Verification  
Logic Design  
System Design & Verification  
Digital Implementation  
Manufacturability signoff  
PCB & IC Packaging  
Services  
Education Services  
Cadence Academic Network  


Quick links
 

Cadence blogs

 
Events








   

EDA360
The way forward for

electronic design
 

 

 

 


 Twitter
 
 
 
 
 

Upcoming Events

TLM Tech Talks
Leveraging the experience of Cadence R&D and architects, discover the benefits of the TLM-based design and verification methodology, hear about real customer case studies, and learn how you can incrementally adopt this approach into your existing methodology.
Espoo, Finland - 24th May 2010
Bracknell, England - 25th May 2010
Munich, Germany - 27th May 2010

Register now>>

ARM Cortex -M0 Workshop for Analog Mixed Signal Designs
During a full day workshop, ARM and Cadence will take you through all the design considerations to successfully architect and tape out a Cortex-M0 processor-based microcontroller for a mixed signal application. This free workshop will be held in Paris on 27 May, from 8:45am to 16:45pm. Register here >>

2010 Technology Updates for Encounter Digital Implementation System and
Cadence Logic Design Solution
Cadence is hosting a major series of seminars across Europe that include in-depth scenarios of digital design challenges that you may be struggling with today, as well as the latest features and functionalities of the Encounter Digital Implementation System and the Cadence Logic Design Solution that will help you overcome such challenges. The series kicks off on 8th June 2010. View the full list of dates and locations here

Back to top


Cadence in the news

Cadence to Acquire Denali

Cadence Accelerates SoC Realization, Reduces Costs With New Open Integration Platform

Cadence Issues Blueprint to Battle 'Profitability Gap'; Counters Semiconductor Industry's Greatest Threat

Back to top


Functional Verification

Cadence Contributes Technology to Boost Verification of Complex Mixed-Signal Chip

Cadence has contributed to the Accellera standards organization new technology that can help engineers conduct faster and more thorough functional verification on complex mixed-signal SoCs. Cadence® donated a set of extensions to the wreal feature of the Verilog-AMS real numbered modeling capability. These Cadence extensions are designed to improve accuracy and offer better plug-and-play with analog models. Wreal enables engineers to conduct functional verification on these SoCs at digital speed. Faster and deeper verification can translate to fewer re-spins and faster time to market.

Read more >>

Back to top




Custom Design

Virtuoso Surveys
We invite you to take a moment and complete two short surveys to help us develop and deliver future Virtuoso software and service enhancements, tailored to your needs
.
Virtuoso® QuickSurvey: HW/Thin Client
This quick survey gathers information about desktop hardware and thin client software utilized by Virtuoso users at your company site.
Virtuoso® QuickSurvey: Videos
This quick survey gauges your interest in, access to, and current use of Virtuoso videos currently hosted by Cadence Online Support (formerly SourceLink).

Things You Didn't Know About Virtuoso: ADE XL Specs, Corners and comparison of Corner runs

ADE XL: Setting Specifications & Running Simulations
Specification types, Run toolbar, viewing specs in Results panel, output formatting (digits, units, notation--IC 614), using the Evaluate button
ADE XL: Setting Up & Simulating Corners
Creating temp. & voltage corners, creating and using model groups, running corners & sweeps, working with simulation history results, viewing corners results, plotting waveforms from individual corners
ADE XL: Spec Comparison
Comparing 2 corners runs after a change in the circuit, comparing results from 2 swept parameter values across corners

Virtuoso Accelerated Parallel Simulator (APS) won EDN Innovation Awards in its category
The category was for EDA: Front-End Simulation and Database Tools, and the competitors were:
1.BOM Manager Version 4 bill-of-materials-management tool, SiliconExpert Technologies
2.MVSIM voltage-aware cosimulator, Synopsys
3.Virtuoso Accelerated Parallel Simulator, Cadence Design Systems 4.ZeBu-Server emulation system, EVE

Read more at EDN.com >>

Back to top



Logic Design

ChipEstimate.com Announces New IP Partners

With More Than 27,000 Registered Users, Leading IP Portal Offers a Broad Catalog of IP from More Than 200 Companies

New members joining at the Prime Plus partner level include True Circuits, Inc., Virage Logic and Xilinx. New members joining at the Prime partner level are Alvand Technologies, Boeing, ChipStart, Evatronix, HDL Design House, Imagination Technologies, National Semiconductor, NTLab and Snowbush IP. Twelve additional companies are being added to the Choice partner level.

Read more >>

Back to top


System Design & Verification

Cadence Debuts Verification Computing Platform, Accelerating Time and Improving Quality of System Development

New Unified, Scalable Verification Platform Increases Productivity of Design Teams, Supports Next-Generation SoC Designs. Developed to support next-generation designs, the highly scalable Palladium XP verification computing platform lets design and verification teams bring up their hardware/software environment faster and produce better quality embedded systems in a shorter time.

Read more >>

Palladium XP

Back to top


Digital Implementation

User Review of The Encounter Foundation Flow
This is a guest blog from John McGehee. John is an independent consultant in Silicon Valley, specializing in EDA application development and design. Read more >>

Signoff-Driven Implementation = Consistent and Convergent = Predictable and Efficient
Digital designs are reaching 10s of millions of instances, which makes efficiency of the overall digital implementation and signoff flow critical to ensure predictability in the design schedule. A major stumbling block that can be a real threat to that predictability is iterations between different stages of the design flow. There are multiple reasons why this happens but one that should not happen is because you have two design stages giving you two different answers with the same set of data. Read more >>

IR Drop Analysis: It's Not Really Necessary, Is It?
Blogger Pete McCrorie was recently asked by an engineering manager if running IR drop analysis was really necessary. The argument to support his question was that his engineering team always over-designs the power rails, and so the risk of getting high IR drop was so small that analysis was not required. Read more >>

Back to top


Manufacturability signoff

Automatic Elimination of Lithography Hotspots Using 2D Pattern Detection and Correction

Read this AMD presentation from CDNLive! Silicon Valley 2009.

Back to top


Education Services
What´s new in
Virtuoso 6.1.x?
Latest releases in
Digital IC Design
Language & Methodology Highlights

Become proficient in the IC6.1.3 release:
- Virtuoso Analog Design Update v6.1.3
- Virtuoso Physical Design Update -v6.1.3

Get trained in the latest Encounter Digital Implementation release:
- Encounter RTL Compiler v9.1
- Floorplanning, Physical Synthesis, Place and Route (Flat)-v9.1
- Floorplanning, Physical Synthesis, Place and Route (Hierarchical)-v9.1

Latest additions to our portfolio:
- SystemC Synthesis using C-to-Silicon Compiler - v10.1
- SystemC Transaction Level Modeling (TLM2)

New Schedule June to December 2010 now available.
Contact us to receive a free copy.

 

Back to top





PCB & IC Packaging

Read the latest PCB blogs!

What's Good About SCM and Packageable Schematics? The Secret's in the SPB16.3 Release!

What's Good About DEHDL Alignment?

Back to top


 


©2010 Cadence Design Systems, Inc. All rights reserved.

To unsubscribe, please click here