To display this email in a browser, please click here
Season's Greetings from Cadence eEuronews
December 2010/January 2011 Issue
 In this issue
In the news
Functional Verification
Logic Design
System Design and Verification
Custom IC and RF Design
PCB and SiP design/IC packaging
Digital Implementation
Manufacturability Signoff
Academic Network
Education Services
 Quick links
Cadence blogs
Events
Twitter
Season's Greetings and Best Wishes for a prosperous New Year from the Cadence EUROPE team.

In this last issue of 2010, I would like to bring your attention once again to the deadline of our Call for Papers for the next CDNLive! EMEA user conference. All users that send us their paper abstracts by Dec 15th will participate in an iPod nano prize draw. So don't miss to submit your abstract now! If you haven't had the chance to hear from some of your peers who presented this year, have a look at the CDNLive! Multimedia Channel.

More than 550 customers from across Europe took the chance to attend one of the offered EDA360 Tech on Tour seminars. Half of them attended the Mixed-Signal Silicon Realization seminar to learn about the latest technologies of Virtuoso IC 6.1. This is an outstanding number and reflects the readiness of the engineers to deploy and master the latest design technologies.

The next issue of eEuronews will be distributed in February 2011. I wish you all a successful year ahead.

Best regards,

Wolfgang Stronski
EMEA Marketing Director at Cadence

 Cadence in the news
Open-Silicon Achieves Ultra High Performance Using Cadence Silicon Realization Technology to Tape-Out Breakthrough 2.4 GHz ASIC Processor
Read More >>

Outlook 2011: A new vision for the EDA industry - By John Bruggeman
New Electronics, Nov 3, 2010
Read More >>

Israel flag "Play it again Semi!" in Hebrew
The Marker, Nov 11, 2011
Read More >>

Back to top ↑


 Functional Verification
The SoC Verification Gap

There is a HUGE gap in how SoCs are verified today vs. what is needed in order to have a scalable and efficient SoC development process. The challenge of bringing a new SoC to market is exactly why a colleague of the phrase "time to integration" has been coined.. Today's SoCs, are all about integration - integrating IP blocks, integrating analog content, and integrating more and more of the software stack. While it is true that all of this integration work still includes design challenges, the bigger issues around improving time to integration are centered on improving the entire SoC verification process
Read More >>

CADENCE BLOG - Low Power Verification

If you have been building chips for years and the growing complexity means you just can't tolerate simple tool-to-tool flows and group-to-group barriers any more. SystemC and RTL in the same low-power simulation? Got it. Mixed-signal? Yep. Every team with fingers in the power intent? For sure. Silicon Realization is real to you because you're living it, but you need more from EDA so you're demanding "Cadence Low-power Verification: Tear Down These Walls!!"
Read More >>

Back to top ↑


 Logic Design
CADENCE BLOG - How Metal-Only ECOs Save Full Silicon Respins

As anyone who has been through the process knows, a complete (all layer) silicon respin is extremely time-consuming and costly. At the recent CDNLive! Silicon Valley, Ranjit LoboPrabhu, back-end lead implementation engineer at Netronome, discussed a better approach. In a paper co-authored with Bob Dwyer of Cadence, LoboPrabhu described a flow that can implement "mega ECOs" in just a few metal layers, with huge cost and time savings compared to full respins.
Read More >>

Back to top ↑


 System Design and Verification
CADENCE BLOG - Broadcom Presentation Shows Value of Transaction-Based Acceleration

At CDNLive! Silicon Valley 2010, the joint paper from Broadcom and Cadence, titled Transaction-Based Acceleration: Strong Ammunition in any Verification Arsenal, showed evidence that simulators are running out of steam for system level simulations. At Broadcom, simulators certainly maintain their value from sub-block to chip-level simulations, providing their users with tremendous debug and ease-of-use efficiencies. However, the lowered performance profile for simulations at the system-level are impeding Broadcom's ability to meet their tight schedules while verifying and producing high-quality products. After evaluating several verification solutions available in the marketplace, Broadcom has now added transaction-based acceleration to their verification arsenal.
Read More >>

CADENCE BLOG - System Bring-Up - THE Critical Path in the System Development Process

The electronic industry is moving from hardware-defined products to software-defined and application-driven products. As a result, product differentiation shifts to software content while hardware platforms and their development processes increasingly become increasingly commodities. Time-to-market pressures and the trend toward software-defined product functionality make the traditional sequential process - SoC/System development followed by board and device development followed by software development - obsolete.
Read More >>

Back to top ↑


 Custom IC and RF Design
New Virtuoso MMSIM 10.1 release available!

The MMSIM 10.1 release continues to provide advanced technologies for analog and mixed-signal verification delivering productivity and predictability for realizing your silicon.

What is new?

  • Introduced an APS single core package enabling every day simulation for your analog block design
  • APS got faster again with single core and multi-core on your challenging circuits
  • APS-RF for advanced RF analysis with multi-threading - fast envelope analysis delivering extreme performance for simulation of power amplifier circuits; shooting Newton technique for non-linear circuits
  • Reliability analysis native to Spectre and APS giving significant capacity and performance boost
  • UltraSim delivering improved performance for EM/IR analysis
  • UltraSim's first release of new FastSPICE technology delivering accuracy and usability targeting advanced node memory designs - limited production
  • Synchronization of MMSIM 10.1 and IUS 10.2 for AMS Designer
  • IUS 10.2 AMS Designer with usability improvements for ADE OSS
For more information on Virtuoso MMSIM 10.1 please contact Robert Schweiger

Video Demo -- Increase Simulation Accuracy and Efficiency With SpectreMDL

MDL is an immensely powerful feature in our simulators that allows designers to run better simulations quicker.
View quick demo to get started >>

Back to top ↑


 PCB and SiP design/IC packaging
A Shorter, Predictable Design Cycle for Complex PCBs - Dynamic Phase Control
By Hemant Shah

This is the second in a series of blog posts about making your design cycles shorter and more predictable for increasingly complex PCB designs. In my last post I talked about using ECSets and Topology Apply capabilities for high-speed standards based interfaces such as DDRx and PCI Express.
      Continuing on that theme, implementing high-speed signals can be a challenge as the delay tolerances shrink and matching requirements increase. Take the example of differential pairs on advanced standards based interfaces (PCI Express generation two and three). A few years ago, static phase tolerance from driver to receiver was good enough. Now, with newer interfaces, differential pairs cannot be out of phase over a certain length.
Read more >>

Back to top ↑


 Digital Implementation
Less Pessimism by Applying Design-Specific OCV Analysis
Michio Komoda, Renesas

Traditional deterministic static timing analysis (STA) is widely used in digital design today. But with smaller process nodes, variation increases, which makes the STA approach very pessimistic. Statistical static timing analysis (SSTA) can reduce this pessimism in STA by analyzing the aggregate probability of delay over a path that reduces overall pessimism. However, the concept of statistical timing analysis is quite different from traditional deterministic STA methods. This makes the practical application of this technology more difficult. The design-specific OCV (DS-OCV) technology available from Cadence helps to address this difficulty by simplifying the design flow while still leveraging the pessimism-reducing benefits of SSTA. This presentation introduces the DS-OCV concept and details the experiences of Renesas Electronics in applying it in a production design flow.
View session or download file >>

Access to technical sessions requires logging in with your Cadence.com account

Back to top ↑


 Manufacturability Signoff
Convergent Silicon Realization via Early Elimination of Yield Detractors Using Integrated DRC+ in Digital and Custom Implementation Flows
Vito Dai, GLOBALFOUNDRIES

With increasing design cost and time-to-market pressure, a redesign or several weeks delay because of poor yield may mean the financial death of a project and the subsequent loss of market window opportunity.
      At 28nm and below, manufacturing challenges are such that minimum DRC rules fail to capture too many potential yield issues, whereas global application of relaxed DRC rules causes an unacceptable increase in design area. GLOBALFOUNDRIES recently announced an innovative DFM approach called DRC+ that is more than 100x faster than traditional litho simulation. DRC+ leverages fast 2D pattern matching to search designs for potential yield detractors and mark them for fixing with relaxed DRC rules.
      This paper will describe what, when, why, and how designers incorporate DRC+ into an existing digital implementation flow as part of DFM signoff at 28nm and below. With Cadence pattern matching and automated fixing built into Encounter technology, designers can quickly and efficiently identify and fix DRC+ errors, thereby avoiding potential manufacturability issues down the road.
View session or download file >>

Access to technical sessions requires logging in with your Cadence.com account

Back to top ↑


 Academic Network
Academic Network Update

2011 will mark the fourth time that the Academic Network has come together with industry attendees at this conference. Papers for the academic track will be selected by the Academic Committee which comprises individuals from academic institutions and from Cadence.

The topics of interest include (but are not limited to):

  • Outstanding industry and university collaborations
  • Outstanding courses, laboratories and design projects development
  • New concepts in teaching
  • Outstanding curricula in Micro- Nanoelectronics education
  • Education for entrepreneurship in microelectronics
  • Emerging fields in design and technology
  • Microelectronics teaching in the future
  • Long distance and continuous microelectronics education
  • Educational infrastructure: design and IP libraries, CAD tool access
  • This is a fantastic opportunity to interface between industry and academia and to discuss future challenges with the academic community.
Submit your abstract now
Back to top ↑


 Education Services
New EMEA Training Schedule for H1 2011 released
Download it here or contact us to receive a printed copy.

Last seats in December classes available!
Contact your local training team or have a look at cadence.com/training/eu.

Latest Training Releases New Back to top ↑
©2010 Cadence Design Systems, Inc. All rights reserved.

To unsubscribe, please click here