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April 2010 Issue
In this issue
Welcome to the April issue of eEuronews!
Today, I cannot resist talking about CDNLive! EMEA, our regional user conference and networking highlight of the year, to be held in Munich from May 4-6.
Please find my personal invitation and some good reasons why you shouldn't miss the event by clicking here.
Amongst a rich technical program of user presentations, keynotes, techtorials, demos and roadmaps from Cadence, you have the opportunity to hear and exchange ideas with hundreds of Cadence® technology users.
An additional academic track offers the opportunity to discuss outstanding work in education and research from universities.
To receive the latest updates on CDNLive! EMEA and all other events in our region, you can also now follow us on Twitter.
Wolfgang Stronski Marketing Director EMEA, Cadence Design Systems
p.s. As every year, you can count on some special entertaining elements throughout the evening event of Wednesday 5th May
Charlie Huang, senior VP and Chief Strategy Officer, Cadence Design Systems talks to Electronics Weekly about important trends in design tool architectures, how EDA is helping tackle complexity in analog and multicore designs, and how the industry is reacting to adapt to the current economic conditions...
An Inside Look At The Unified Coverage Interoperability Standard
A standard is quietly emerging to help verification engineers deal with coverage information from different sources - and if that's a concern for you, there's still time to get involved. The Accellera Unified Coverage Interoperability Standard (UCIS) committee is developing a draft standard for an API that will allow engineers to merge coverage data from different verification tools into a single database. This includes tools from different vendors as well as different types of tools (specifically, simulation and formal verification).
Chipsbank Adopts Cadence Incisive Xtreme III System to Boost SoC Verification Performance
Chipsbank Microelectronics Co., Ltd., a leading fabless IC design company based in Shenzhen, China, has adopted the Cadence® Incisive® Xtreme® III system to accelerate the RTL design process with a verification flow for its next-generation digital consumer and networking chips. "We saw significant performance improvement after adopting Cadence Xtreme III-it speeds up the verification time over 500 times," said Henry Zhang, CEO of Chipsbank. "We are also impressed with its usability and debugging capability, which help greatly shorten the verification cycle of our chips for the highly demanding consumer market. We are looking forward to collaborating with Cadence on future projects, including 65-nanometer implementation and design services."
Bringing MEMS Into the IC Design Flow: paper by Stephen Breit, Coventor and
Randolph Fish, Cadence Design Systems Read paper >>
Bringing MEMS Design To The Mainstream: Blog by Richard Goering: Read more >>
Coventor MEMs workshop, Paris, May 17-18 Cadence will present a paper on MEMS - IC co-optimization using ADE-GXL - "Essential tools for MEMS + IC Systems"
Day 1: Key experts will give a talk about their work, and vision. Day 2: Hands-on training on MEMS+.
MEMS+ is the new Coventorinnovative platform allowing easy MEMS+IC co-design under existing simulation environment such as Cadence. This workshop will address MEMS & IC design challenges and solutions, and gives a perfect opportunity for networking.
Speakers from companies including STMicroelectronics, Schlumberger, Cadence Design Systems, ESIEE, LNE, Coventor... The event is free of charge, but seats are limited.
Jack Erickson (Product Marketing Cadence RTL Compiler) recently read a well-thought article trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). The article lists lots of factors that enabled the mainstream shift from gate-level to RTL, and sketches out a similar list of what would be required to move from RTL to TLM. Having worked in the logic design area of EDA since roughly 1993 Jack would like to offer his own view on this transition.
Q&A: What Cadence Has Learned About High Level Synthesis
With the recent release of Cadence C-to-Silicon Compiler, Cadence has joined the rapidly growing high-level synthesis (HLS) marketplace. In this interview Mike "Mac" McNamara, vice president and general manager of the Cadence Systems Software Group, talks about what Cadence has discovered about HLS and its users.
Accelerating Media Processor Development using Simulation Acceleration Techniques-Lessons Learned
Learn how Sigma Design Inc. engineers have worked extensively with Cadence on two simulation-acceleration techniques referred to as "signal-based acceleration" and "transaction-based acceleration" and how these concepts were applied for the latest design at Sigma Design.
This year DATE (Design, Automation and Test in Europe) was in snowy cold Dresden, Germany, March 8th-March 12th and offered several 3DIC topics during the conference. I heard someone say "How did 3D with TSVs become hot from cold just so quickly?" In fact it did. Last year when I was following this technology I had found the design community to be hesitant in the feasibility of this technology in the beginning with lots of secretive projects in the pipeline. Suddenly by the end of last year, several IDMs, foundries, Cadence, and other EDA vendors were sharing methodologies and flows around 3D. There is now at least one discussion on this topic, at every industry conference, in various forms - panel, paper, etc.
Cadence Design Systems is offering design for manufacture analysis for 28nm and 32nm process technologies in the latest release of its Encounter Digital Implementation (EDI) system-on-chip design tool. The tool will be used for the design of high complexity SoCs with hundreds of millions of gates, including hundreds of IP elements and embedded processors.
To address the design complexity issues of this class of device EDI System 9.1 combines automatic floorplan synthesis, data abstraction modelling and concurrent macro- and standard cell placement. This is achieved in a process the company calls "design exploration" which involves the automatic examination of thousands of combinations of design variables, option settings, floorplan architectures, and physical implementation approaches in parallel.
"This exhaustive examination allows users to fully explore the range of design possibilities," said Cadence. "Since foundries mandate DFM checks in the physical design flow at 40nm and below, built-in, foundry-certified DFM analysis is a must-have at these nodes," said Cadence. An integrated DFM capability will offer pattern intelligence and filtering in the interconnect routing phase of the design process.
Cadence Expands PCB Portfolio with Taray Acquisition
Cadence announced that it has acquired Taray Inc., an industry leader in technology for integrating multiple large, complex field programmable gate arrays (FPGAs) into printed circuit board (PCB) system designs. By embedding Taray's patented FPGA synthesis technology throughout the PCB design process, Cadence will provide customers with a platform that boosts productivity and accelerates design authoring and implementation of FPGA-based PCBs.
Cadence Teams with AcAe to Accelerate Customer Transitions to Allegro PCB Products
Cadence announced that it is teaming with American Computer Aided Engineering (AcAe), a dedicated CAD/CAE support services provider and design bureau, to assist customers transitioning from competing legacy CAD systems to Cadence® Allegro® PCB technologies and methodologies. With 24 years of experience in the electronic design automation industry, AcAe is helping Cadence PCB customers meet time-to-market commitments with design services and ease new product adoption as they migrate to and deploy Cadence Allegro technology.