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April 2012 Issue
 In this issue
In the News
Cadence Events
Functional Verification
Custom IC Design
Manufacturability Signoff
Low Power
Digital Implementation
IP News
PCB and SiP design, IC packaging
System Design and Verification
Education Services
 CDNLive! EMEA
 Media Partners
cdn LIVE EMEA 2011
cdn LIVE EMEA 2011
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Welcome to the April edition of eEuronews in 2012!

Only 4 weeks to go to CDNLive! EMEA. Registration is up and running and we are looking forward to seeing you all soon. This year the agenda is packed with activity and you can choose from a variety of technical themes that will inspire you how to tackle your specific design challenges using new approaches and the latest technology.

We are also very pleased to announce that Luc Van de hove, CEO of imec, will deliver the industry keynote in the morning of May 15. Here you can get a sneak preview of another keynote that will be delivered by Tom Beckley, VP R&D, Custom IC and Signoff at Cadence, view this video:

In addition to the keynotes and user-presented technical papers, more than 20 companies will be showcasing their new products and services at the Designer Expo.

cdn LIVE EMEA 2011
We also arranged for the Cadence Academic Network to host an academic track providing a forum to present outstanding work in education and research from groups or universities.

This year CDNLive! EMEA will also offer mobile networking at the event. We will install a new service that will help attendees connect, share and meet up with other attendees that share the same interests.

Our focus has been to put together an excellent event for you. But it doesn't stop there, in order to complete the experience and continue the tradition of offering a relaxed atmosphere, a special evening event with music, food and many surprises, has been organized for attendees on the evening of May 15. Don't miss it!

To register and to get all conference details click here.

Wolfgang Stronski
Marketing Director EMEA, Cadence

 News
Cadence Low-Power, Advanced-Node Digital Technology Incorporated Into SMIC 40nm Reference Flow »

Cadence Named a Winner of the Prestigious UBM Electronics ACE Awards in the Software Ultimate Products Category »

Cadence Announces Support for New Interface Verification IP for Development of Cloud Infrastructure »

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 Cadence Events
cdn LIVE EMEA 2011
CDNLive! EMEA 2012, Munich, May 14-16, 2012
CDNLive! brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.

Event details »

Webinars: Industry Leaders Unveil Shared Vision for 20nm
Gain Clarity to Succeed at Advanced Nodes

1 May 2012 - 3 May 2012: Attend and enter to win an Apple® iPad

If you are designing or planning to design at 20nm process technologies, don't miss this webinar series. At 20nm, there are multiple new and disruptive design and manufacturing discontinuities that must be understood and handled to ensure successful silicon.

In this webinar series, ecosystem leaders will walk you through 20nm challenges and offer their experiences, guidance, and recommendations to help you gain clarity on how to succeed at advanced node design.

Event details »

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 Functional Verification
cdn LIVE EMEA 2011 Cadence announced the support for two popular protocol standards used in cloud computing applications, 12Gb/s SAS and NVM Express, to the Cadence Verification IP (VIP) Catalog. The expanding VIP Catalog is helping leaders in the networking market, like AppliedMicro, to deliver the systems and SoCs powering cloud-based computing.

Get all information here »

Hardware Simulator Performance Scaling to Meet Advanced Node SoC Verification Requirements
By Amit Dua, Adam Sherer, and Umer Yousafzai - Cadence

Because of its flexibility, hardware simulator-based verification is expected to scale with design complexity. Continuous innovation has enabled hardware simulators to reduce both memory and overall turnaround time. The Cadence® Incisive® Enterprise Simulator not only embodies these characteristics, but also provides the new controls, technologies, and methodologies necessary to meet SoC verification performance requirements at sub-40nm. This technical paper examines the Cadence systematic approach to optimizing verification performance and productivity.

Download White Paper »

Functional Verification Webinar Series 2012

Hot tips from Verification experts - attend technical webinars on advanced verification approaches

View webinar schedule and topics here »

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cdn LIVE EMEA 2011

 Custom IC Design
Digital and Analog Verification - Round Peg in a Square Hole?
Blog by Richard Goering

Recently I wrote about a panel discussion that looked at ways of bridging the gap between analog and digital design. This blog post resulted in a lengthy discussion in a LinkedIn group that brought up the topic of verification. One commentator noted that analog and digital designers have very different interpretations of "verification," and concluded that "people have been trying for years to squeeze the round analog peg into the square digital hole."

Read Blog »

Things You Didn't Know About Virtuoso: Change is Here to Stay

Speaking of variation - and isn't everyone these days - something strikes me in reading about all the powerful and elegant features of corners management and statistical analysis. After all the simulations are run and the results are presented, unless you've managed to hit a bullseye on the first design you tried (good luck with that), you're probably going to have to change something in the circuit in order to turn all those lights green. (Of course, you'll only see that lovely green coloring - or the not-so-desirable yellow and red coloring -if you're using specifications in ADE XL).

Read Blog »

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 Manufacturability Signoff
Modeling Stress-Induced Variability Optimizes IC Timing Performance
By Nishath Verghese, Ramez Nachman, Philippe Hura, Cadence

Many design teams migrate to advanced IC process nodes to increase perfor¬mance while reducing area and power. Timing performance and predictability can be compromised, however, if there's too much systematic variability. Fortunately, systematic variability can be modeled and mitigated if one under¬stands the causes. A leading cause of systematic variability at 45 nm and below is the application of mechanical stress to transistors.

Download White Paper »

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 Low Power
Don't Blow Up Your Chip on the Tester!
By Pete Hardee, Cadence

What can happen - if you use automatic test pattern generation (ATPG) vectors that aren't power-aware -- is that test power can end up being several times higher than the functional power the chip was designed for. The problem is too much switching. When you load the scan chains, flip-flops trigger. When you capture the responses, they trigger again. Too much switching activity can overstress the chip, potentially damaging it or, worst case, blowing it up.

Read blog »

Jan Rabaey's remarkable short course in Low-Power Design Essentials, Part 1
low-powerdesign.com

At the end of January, UC Berkeley EECS Professor Jan Rabaey gave a comprehensive one-evening course in low-power design essentials to about 100 people attending a meeting of the Santa Clara Valley chapter of the IEEE Solid State Circuits Society. It was a comprehensive presentation, given the amount of time available, and it extended information in Rabay's book, Low Power Design Essentials, published by Springer in 2009. In this blog post and subsequent posts, I will attempt to summarize more than two hours of Rabaey's rapid-fire presentation.

Read blog »

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 Digital Implementation
The Technology Behind Encounter 11.1 - Optimization for GHz, Giga-Gate, and 20nm Design
Blog by Richard Goering

Realizing that high-performance (GHz range), high capacity (100M+ instances), and 20nm digital IC designs need new tools and methodologies, Cadence has announced Encounter Digital Implementation System 11.1. Here's an inside look at three technology innovations that make it possible - a new optimization engine, a new abstraction technology, and a correct-by-construction approach to 20nm double patterning.

Read blog »

Five-Minute Tutorial: Where To Find More Encounter Digital Implementation (EDI) System Tutorials
We've had some people joining the forum lately that are either brand-new to Encounter Digital Implementation (EDI) system, or are coming back to it after several years away. I thought it would be a good time to highlight some great tutorials for getting started with EDI.

Read blog »

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 IP News
Cadence Delivers High-Performance, Low-Power Design IP Supporting LPDDR3 Memory Standard
Cadence announced the addition of design intellectual property (IP) for the LPDDR3 mobile memory standard to its design IP portfolio. Designed to provide the high bandwidth and low power consumption required by smartphones and tablets, the Cadence LPDDR3 memory IP solution includes integrated controller and PHY support, virtual prototyping, verification IP and Allegro® design-in kits to accelerate implementation and reduce design risk.

Read press release »

A possible roadmap for Wide I/O that leads to 2Tbps of SDRAM memory bandwidth-per device
Cadence Product Marketing Director Marc Greenberg-one of the speakers at last week's EDPS conference held in Monterey, California-spoke about why the Wide I/O SDRAM is probably the "killer app" that unleashes 3D IC assembly into the mainstream.

Read blog from Denali report »

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 PCB and SiP design, IC packaging
FPGA-PCB codesign; a 21st Century approach to integrating FPGAS into the PCB design process
New Electronics - By Hemant Shaw, Cadence

Integrating advanced fpgas on a pcb is becoming increasingly challenging, with issues including generating optimal fpga pin assignments that do not add layers to a pcb or increase the time required to integrate the fpga with the pcb design. Because of this, fpga designers, schematic engineers and pcb designers struggle to create fpga pin assignments that meet the goals for the entire system.

Continue article »

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 System Design and Verification
Extending the Metric-Driven Verification Methodology to TLM
SoC Central.com - By Yosinori Watanabe and Jack Erickson

The electronic design industry has experienced quantum leaps in productivity every time that the abstraction level of design has been raised, as was the case when RTL synthesis enabled verification to move from the gate level up to the register-transfer level (RTL). Design, of course, benefited in the move to higher abstraction, but the biggest benefit occurred with verification, in terms of faster simulation and easier debug. Today we are experiencing a similar shift.

Read article »

Building a NAND flash controller with high-level synthesis
EETimes.com - By Tung-Hua Yeh and Jen-Chieh Yeh, Industrial Technology Research Institute; and Qiang Zhu, Cadence

High-level synthesis (HLS) is a key technology that links electronic system-level (ESL) design to register transfer-level (RTL) implementation. In addition to automating the ESL-to-RTL design flow, HLS enables efficient design space exploration that helps designers quickly achieve a micro-architecture that meets their goals. However, traditional HLS technologies were mainly applicable only to datapath-dominated design and were not effective for control-intensive design. Also, traditional HLS technologies required specific design styles and use models to achieve good quality of results (QoR).

Read article »

Virtual System Platform Takes Home Coveted ACE Award for Software of the Year

At the 2012 UBM Electronics ACE Awards held Tuesday, March 27, the Cadence® Virtual System Platform was named a winner in the Software of the Year category. The UBM Electronics ACE Awards is the result of the EE Times' Annual Creativity in Electronics (ACE) Awards and EDN's Innovation Awards joining forces to honor the products, people, and companies that are revitalizing the electronics industry and enhancing our lives. The ceremony took place at The Fairmont San Jose during DESIGN West (formally the Embedded Software Conference).

Read blog »

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 Education Services
Register Modeling in UVM
Education Services at CDNLive! EMEA 2012


15th May 2012, 15:00-17:00. Presenter: Brian Dickinson

In this Register Modeling in UVM session, we will explore the uvm_reg basics and give you a hands-on opportunity to develop simple verification for the registers in a Design Under Test (DUT) using a pre-written UVM verification environment.

This session is aimed at novice UVM users who wish to understand and appreciate the basics of register modeling with UVM.

Full Agenda »
Register now »

new in our training portfolio

Using Virtuoso Constraints Effectively vIC 6.1.5
This course is a practical examination of the way to set specific rules in the schematic that will be transferred to the layout design.

Analog-on-Top Mixed Signal Implementation
This newly developed training course targets experienced Analog Layouters and CAD Engineers who aim to implement designs in a Mixed Signal Environment. Within this 3 day training you gain experience in the area of Mixed Signal Implementation.

Cadence Training Brochure 2012

Training at a glance - discover our flexible training delivery methods - Live, Virtual and Online (iLS) trainings, and browse through the comprehensive Learning Map of your interest. Download the PDF version here, or contact us for a complimentary printed copy.

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