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November 2011 Issue |
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Welcome to the November issue of eEuronews!
In the last issue we briefly mentioned the upcoming launch of the CDNLive! EMEA Call for Papers. The submission page is now open and the deadline for your entry is Dec 14, 2011. Don't miss the chance to tell your story and submit an abstract for consideration at the 2012 conference.
In recent news Cadence and ARM reported about a milestone tape out of a 20nm ARM Cortex™-A15 MPCore processor. Cadence and ARM solutions include a comprehensive set of optimized tools for ARM processor and physical IP; expert design services; production-proven flows and reference methodologies from embedded Linux to GDSII; and a full suite of chip, package, and board co-design capabilities. Visit our special Cadence and ARM collaboration page for more information.
This month we also launched the Technology on Tour On-Demand service. You can sign up for a live chat session to watch the video and engage with technical experts and other peers during scheduled times. As always, we are interested in hearing from you about your experience.
Best regards,
Wolfgang Stronski
Marketing Director EMEA, Cadence
P.S. Don't miss our Club Formal event in Cambridge, UK, on Nov 30, 2011 |
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| Cadence Events |
EDA360 Technology on Tour: Mixed-Signal Silicon Realization
Join us for this 1-day free seminar focusing on analog/mixed-signal design, implementation, and verification.
Explore the latest technologies and integrated flows from Cadence that will help you design higher performance chips and systems more efficiently. This year we will have a focus in all sections on best practices discussing and showing detailed demos of many front-to-back aspects of custom/analog design.
• 09 Nov 2011 - Leuven, Belgium
• 10 Nov 2011 - Eindhoven, The Netherlands
• 15 Nov 2011 - Milan, Italy
• 16 Nov 2011 - Grenoble, France
EDA360 Technology on Tour: Silicon Realization - Club Formal
Don't miss the chance to extend your formal verification expertise and learn more about general advances in the field, the Incisive Formal and Enterprise Verification roadmaps in particular, and to network with other Formal and ABV power users.
• 30 Nov 2011 - Cambridge, UK
Watch Now!
Watch technical presentations and demonstrations on-demand and learn how to overcome your design challenges with the latest capabilities in Cadence custom/analog, digital, and PCB design technologies.
Sign up to Chat Live!
Sign up for a live chat session to watch the video while chatting live with technical experts and other viewers during scheduled times.
Digital Track - click here »
PCB Design Track - click here »
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| System Design and Verification |
Xilinx and Cadence Introduce an Extensible Virtual Platform to Enable Software-Centric Approach for Embedded Software Developers
Xilinx and Cadence have teamed up to develop the industry's first virtual platform to enable system design, software development, and testing of Xilinx Zynq™-7000 Extensible Processing Platform (EPP) based systems in advance of hardware availability. This solution further enhances the development environment being put into place for Xilinx's ARM® processor-based processing platform and changes the development flow for embedded designers, enabling software content to drive hardware design.
Press release »
Video: TSMC and Cadence Address System-Level Complexity with the TSMC ESL Reference Flow 12
View video »
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| Logic Design |
Low Power - Si2 Interoperability Guide V2.0 Available for Download
Recently, the Silicon Integration Initiative (Si2) announced the availability of the Interoperability Guide for Power Format Standards V2.0. This is an important milestone of power format interoperability between IEEE 1801-2009 and the Common Power Format (CPF).
This update was triggered by the Si2's CPF 2.0 release earlier this year. CPF 2.0 is a major CPF release on top of the previous CPF 1.1 and 1.0 releases. Many new features were introduced in CPF 2.0. Another major accomplishment of this new version of CPF is that it has some noticeable enhancements to improve the interoperability with IEEE 1801.
Read More »
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| Functional Verification |
Assertion-based verification in mixed-signal design
analog-eetimes.com, Oct 19, 2011
Prabal Bhattacharya and Don O'Riordan of Cadence examine challenges in analog/mixed-signal verification, and evaluate how the assertion-based verification concept can address some of the challenges. They also look at how Property Specification Language (PSL) and SystemVerilog Assertions (SVA) can be used to write complex analog/mixed-signal assertions.
Read article »
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| Custom IC Design |
Cadence Library Characterization Scripts Now Available in New TSMC Reference Kit
New Library Characterization Reference Kit from TSMC Enables Faster Library Re-Characterization
Read press release »
Virtuoso Success Story: IBM and Cadence
"Cadence Virtuoso unified custom/analog flow, including a comprehensive regression test suite and advanced simulation technology tests, reduced our overall SOI model validation cycle time." - Carl Wermer, Advisory Engineer, IBM
Read story »
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| Manufacturability Signoff |
Collaboration is key to making DFM work at 28nm and below
The Way Forward for Electronic Design by Steve Leibson
At the final presentation I attended at last week's Global Technology Forum, Manoj Chacko from Cadence discussed how to get "everything you're entitled to" with In-Design DFM (Design for Manufacturing). Two of the key yield detractors Chacko discussed are yield losses due to CMP (chemical mechanical polishing) and LDE (layout dependent effects). CMP is an abrasive manufacturing step used to re-planarize the top of a silicon wafer to prepare it for the next layer and it's a key process that enabled the use of multiple copper interconnect layers. During CMP, a thick additive copper layer erodes away until only the desired interconnect wires-set into trenches in an insulating layer-remains. This is the so-called Damascene process named for the intricate metal inlay work and the patterns that appear on swords made famous in ancient Damascus. Unfortunately, CMP can cause a number of problems that result in yield loss.
Read more »
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| Digital Implementation |
A Look at 20nm Design Challenges and Solutions
Blog by Richard Goering
The 20nm process node promises tremendous advantages in power, performance and design capacity, but also raises tough design challenges. These challenges include increased timing and power variability, complex layout rules, and incredibly large designs with massive amounts of IP. A major new challenge at 20nm is the requirement for extra masks (double patterning) to make existing lithography work at this advanced process node.
View blog »
Samsung and Cadence Announce Production of Breakthrough 32nm HD Digital Camera SoC for Ambarella
Leading Technology Companies Join Forces To Deliver Competitive Advantage in Performance, Power, and Time to Market for Advanced Node SoCs.
Press release »
Five-Minute Tutorial: Finding EDI Videos
Blog by Kari Summers
I've seen a few requests in the forums asking about EDI videos. Today I will show you how to find them on the Cadence Support website.
View blog »
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| PCB and SiP design, IC packaging |
What's Good About Single Mode Operation in DEHDL? The Secret's in the 16.5 Release!
Blog by Gerald "Jerry" Grzenia on November 1, 2011
Due to architectural changes in SPB16.5 Design Entry HDL (DEHDL), we no longer require various modes of operation -- such as Hierarchy mode, Expanded mode and Occurrence Edit mode. There will be no need to change modes while working on the schematic since the explicit need for design net listing and design expansion is removed. This is a HUGE simplification from prior releases!
Read blog »
DACH Region:
Cadence und FlowCAD laden zum eintägigen Hands-On DDR3-Workshop ein, wo die unterschiedlichen Anforderungen an z.B. Timing Budget, Signalqualität, Layer-Stack-Up und Auswahl der Bauteileinstellungen systematisch erarbeitet werden. Nach einer einleitenden Theorie werden Beispiele konkret in der Cadence Tool-Umgebung veranschaulicht.
13. Dezember 2011 in Feldkirchen bei München
Zur Anmeldung »
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| New Cadence Academic Network Page |
New Cadence Academic Network webpage is online
It provides all information about the Academic Network. This includes links to our lead institutions and contributors. Furthermore, LinkedIn, being the Academic Network's primary information portal, is introduced.
Additionally, you can find interesting videos from some of our lead institution professors, talking about the academic track at CDNLive!.
Visit the new page »
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| Education Services |
 SPICE Seminar - Learn from the author of "The SPICE book"
Dr. Andrei Vladimirescu will be hosting The SPICE Seminar at our Cadence Munich Training Centre, 29th November - 2nd December 2011 - last seats are available!
The purpose of the course is to help circuit designers better understand semiconductor device modeling, with emphasis on Deep-Submicron (DSM) technology and the operation of a SPICE circuit simulator. The course also addresses the different levels of modeling, structural and behavioral, simulation controls available to the user and new types of analysis such as steady-state, particularly suited for RF design. Participants will have an opportunity to experiment with the various concepts presented in the course on workstations.
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Learn more » |
 Virtual Classes and Dates Available
Virtual Classroom is a web-based environment that allows you to participate in live training events without the need to travel. You listen to lectures, participate in lab exercises, ask questions, and receive feedback just as you would do in a conventional classroom. It saves the hassle, expense, and travel time to a training site.
Have a look at our complete offering at cadence.com/training/eu --> select view: "Virtual Class" 
Upcoming dates:
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