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March 2012 Issue
 In this issue
In the News
Cadence Events
Industry Events
Functional Verification
Custom IC Design
Manufacturability Signoff
Low Power
IP News
PCB and SiP design, IC packaging
Cadence Academic Network
Education Services
 CDNLive! EMEA
 Media Partners
cdn LIVE EMEA 2011
cdn LIVE EMEA 2011
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Welcome to the March edition of eEuronews in 2012!

The countdown has begun to CDNLive! EMEA our annual user conference, taking place in Munich from May 14-16, 2012. The agenda is now available online and the registration is open. cdn LIVE EMEA 2011
Check out the CDNLive! Multimedia Channel where you can listen to some of your peers who will present at the conference and learn more great reasons why you don't want to miss out.

In product news, on March 5, we announced the latest Encounter®RTL to GDSII digital design flow to accelerate your high-performance, giga-scale designs, including those at the latest technology node. The advanced digital flow is built to optimize high-performance chips and drive SoC performance, power and area.

Starting with this issue, we have also added two new sections. The first will be about sharing new insights into Low Power techniques and related topics. The second section will highlight the latest IP offerings from Cadence.

We hope you enjoy the newsletter and look forward to seeing you in Munich this May!

Best regards,

Wolfgang Stronski
Marketing Director EMEA, Cadence

 News
Cadence Accelerates High-Performance, Giga-scale, 20nm Design with Next-generation Encounter RTL-to-GDSII Flow »

Cadence Mixed-Signal Design Product Wins Prestigious ACE Award in China »

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 Cadence Events
cdn LIVE EMEA 2011
CDNLive! EMEA 2012, Munich, May 14-16, 2012
CDNLive! brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.

Event details »

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 Industry Events
System, Software, SoC and Silicon Debug Conference

September 19-20, 2012
Vienna, Austria
Call for Contributions
Deadline April 23!
S4D

The fourth edition of S4D Conference will be held in Vienna, Austria from September 19-20, 2012 and is co-located with the FDL Conference. The conference has evolved from several industry workshops organized by ECSI into the areas of debug and provides a forum for work and standardization efforts related to debug of electronic systems, with a focus on multi-core and multi-accelerator SoCs.

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 Functional Verification
Webinar Report: New Methodology Revs Up Code Coverage Analysis

Most IC verification teams use code coverage as signoff criteria, but they often have limited information about unreachable code. A new "case-splitting" methodology, described in a recently archived webinar, shows how a technique based on formal analysis provides new insight into coverage holes — while requiring no understanding of formal analysis.

Read Blog »

Streamlined Verification Plans Using the Metric Driven Verification Flow
www.soccentral.com
By Henry Nguyen, IP Development Manager at Texas Instruments, Inc. and Jentil Jose, IP Design Verification Engineer at Wipro Technologies


A streamlined verification planning processes is required to meet today's quality and productivity expectations. The Metric Driven Verification (MDV) flow introduced by Cadence provides many enablers to achieve these goals. The MDV flow starts by creating an executable verification plan, namely the vPlan, using a tool feature called Enterprise Planner which is then read into the Cadence Incisive Enterprise Manager tool, along with the coverage results. The term "executable" refers to the idea that Enterprise Manager shows the vPlan with the coverage results and coverage percentages projected onto it.

Read Article »

Best Practices for Selecting and Using Verification IP (VIP)

In the past few years, commercial verification IP (VIP) has been selected for use in an ever greater percentage of verification environments. While VIP has the capability to save considerable time and engineering resources, there are several decisions you need to make in order to optimize the value received. For example, should you buy VIP or build your own, what should you consider in selecting VIP, and how can you make best use of it once you have it?

Read Blog »

Try VIP Software at Your Desktop!

Access VIP Demos on Xuropa - on-line demos with real software at your own pace.

Start your demo »

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 Custom IC Design
Bridging the Gap Between Analog and Digital Design

Analog and digital designers have lived in separate worlds for a long, long time. They use different methodologies and tools, and while digital design is heavily automated, analog design is not. But mixed-signal integration will force this gap to narrow, opening the door to new methodologies and better collaboration, according to panelists at the DesignCon conference Jan. 31.

Read Blog »

Solving Mixed-Signal Power Grid Challenges

Complex analog/mixed-signal ICs pose many power grid design and analysis challenges. Unanticipated IR drop and electromigration problems are commonplace, and they significantly impact circuit behavior. But as a recently archived webinar shows, there are a number of ways to minimize these problems, even for advanced-node, mixed-signal systems on chip (SoCs) with hundreds of millions of transistors.

Read Blog »

New Approaches to Mixed-Signal Verification and Assertions

Nearly all systems-on-chip (SoCs) are mixed-signal, and as complexity grows, new verification techniques are needed. No longer is it sufficient to use traditional analog and digital simulation in isolation - instead, information must flow freely between analog and digital domains to allow a true mixed-signal simulation. A recently archived Cadence webinar showed how this can be done using a mixed-signal parasitic flow, assertions, and low-power verification

Read Blog »

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 Manufacturability Signoff
Customer, Partner DFM Concerns Spur New Methodologies

Design for manufacturing (DFM) may not be as "hot" a topic as it was a few years ago - when there were many independent DFM companies - but foundries and chip design companies are in fact very concerned about DFM at 28nm and below. Some of those concerns have given rise to new technologies and methodologies that will be revealed next week (Feb. 12-16, 2012) in Cadence/customer co-authored papers at the SPIE Advanced Lithography conference in San Jose, California.

Read Blog »

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 Low Power
Secrets of low-power chip design
www.electronicsweekly.com, By Pete Hardee, Cadence

There are ways of making power reduction in your chip design more predictable and they usually involve good power analysis. What are the good techniques for low-power design? Designers have used basic techniques like clock gating and multiple threshold voltage (MVt) library cells for many years. Both techniques are now fairly well automated in synthesis and implementation tools. As we adopted new process nodes and leakage increased, further techniques emerged involving separately supplied power domains.

Read article »

Low-Power Implementation on Freescale Kinetis Family
By Anis Jarrar and John Dalbey, Freescale Semiconductor

Freescale's family of Kinetis SoCs comprise highly integrated, low-power, mixed-signal, 32-bit microcontrollers based on the ARM Cortex-M4 core, with built-in digital signal processing functionality. Kinetis SoCs also use an advanced 90nm split-gate thin film storage Flash memory in its non-volatile memory technology. During a recent Kinetis project, Freescale engineers identified aggressive power targets in no less than 10 different power modes. In addition to this challenge, the first design had 68% new content. Using the CPF-enabled Cadence® Low-Power Solution and its advanced low-power design and implementation techniques, Freescale reduced dynamic power by 30% and static power by 80% in the off state.

Download paper »

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 Digital Implementation
Cadence transforms digital design with ne Encounter RTL-to-GDSII flow
Cadence has announced new technologies and capabilities in its Encounter digital flow, spanning design through implementation and signoff. These latest enhancements enable high-performance, giga-scale, and 20nm designs.

Read more »

Webinar Series: Accelerate Your High-Performance, Giga-Scale, 20nm Design
Cadence transforms digital design with new Encounter RTL-to-GDSII flow. Attend the following webinar series to find out what is new in the latest version of Encounter digital flow and how to:

• Optimize PPA (power, performance, area) on embedded, high-performance processor designs
• Get orders of magnitude compression of the design netlist while still retaining area, congestion, and timing accuracy
• Realize your 20nm design with a unique correct-by-construction, 20nm design, implementation, and signoff methodology with double-patterning technology support

Read more »

Clock Concurrent Optimization Technical Paper

Timing divergence has a critical impact on the economic viability of migrating to sub-65nm process nodes. Clock concurrent optimization (CCOpt) is a revolutionary new approach to timing optimization: it merges physical optimization into clock tree synthesis and simultaneously optimizes clock delay and logic delay using a single unified cost metric. With CCOpt technology, engineers can achieve timing convergence and have a new degree of freedom to design and integrate faster, smaller, lower-power digital chips.

Download technical paper »

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 IP News
Cadence announces design IP for Ultra High-Speed (40/100G) Ethernet
Cadence Expands Proven Ethernet IP Offering with 40/100 Gigabit Ethernet Solution
Accelerates Deployment of SoCs based on Ultra High-Speed Ethernet Standard

Read more »

More information on synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP in Steve Leibson's blog

Continue reading »

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 PCB and SiP design, IC packaging
What's Good About Allegro DFM/DRC Updates? 16.5 Has a Few New Enhancements!
By Gerald "Jerry" Grzenia

Allegro PCB Editor has been enhanced in the 16.5 release with three (3) additional DRC checks and an enhanced DFA utility for a 4th DRC entry, and now allows backdrilling from any layer.

Read more »

What's Good about OrCAD Apps? Symbol and Footprint Creation Just Got a Lot Easier!
By Gerald "Jerry" Grzenia

Creating the symbols and footprints necessary to complete your designs can be a difficult task. Many designers utilize manual processes that are becoming unfeasible with the growing complexity of both the designs and the components used. Secondarily, manual processes are often error prone and provide few efficient methods of error checking. Designers need an efficient way to create schematic symbols and PCB footprints, and validate these models.

The Cadence OrCAD Capture Marketplace and Online Store for Apps provide two new apps, SymbolGen and FootprintGen, to help solve this library creation problem.

Read more »

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 Cadence Academic Network
CDNLive! EMEA 2012 academic agenda now online!

We are pleased to announce the agenda for this year's Academic Track. The format includes research accomplishments and a special session of outstanding collaboration projects. There will be many valuable opportunities to network with academic and industry attendees.

Browse this year's agenda and plan onwards the presentations of your interest.

Go to agenda »

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 Education Services
new New Cadence Training Brochure 2012

Training at a glance - discover our flexible training delivery methods - Live, Virtual and Online (iLS) trainings, and browse through the comprehensive Learning Map of your interest. Download the PDF version here or contact us for a complimentary printed copy.

SPICE Seminar - Learn from the author of “The SPICE book”
Dr. Andrei Vladimirescu will be hosting The SPICE Seminar, 20th-23rd March 2012

The Spice Book cover The purpose of the course is to help circuit designers better understand semiconductor device modeling, with emphasis on Deep-Submicron (DSM) technology and the operation of a SPICE circuit simulator. The course also addresses the different levels of modeling, structural and behavioral, simulation controls available to the user and new types of analysis such as steady-state, particularly suited for RF design. Participants will have an opportunity to experiment with the various concepts presented in the course on workstations.

Learn more »

new In our training portfolio

Logic Equivalence Checking with Encounter Conformal EC v11.1 (Live)
SystemC Language Fundamentals v10.2 (iLS)
Incisive Comprehensive Coverage v10.2 (Live and Virtual)
Allegro FPGA System Planner v16.5 (Live and iLS)

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