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October 2010 Issue |
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Welcome to the October issue of eEuronews!
In this issue I would like to introduce you to the  new blog. The blog will discuss current events and talk about the ins and outs of system design from an "insider" perspective. This is not an ESL blog. It will cover all aspects of IC and system design, including System Realization, SoC Realization, and Silicon Realization. If you are involved in any aspect of electronic systems design, you will find postings of interest to you.
On October 18, we will open the doors for CDNLive! Israel 2010 in Tel Aviv. Join us for an exciting day with keynote presentations, paper and technical presentations.
Don't miss any Cadence seminar, webinar or event that takes place in the EMEA region. Stay updated on all details in our Events section. Our Technology on Tour featuring analog/mixed-signal design will take place in mid-November. We will announce more details in the next newsletter.
We always try to come to numerous locations across the region to make it easy for you to attend. If you or your colleagues can't attend an event of your interest, let us know and we'll seek for ways to get you updated.
Best regards,
Wolfgang Stronski
Marketing Director EMEA
Cadence Design Systems
Stronski@cadence.com
P.S. If you plan to attend the ARM European Technical Conference in Paris on October 21, listen to our technical track or visit our booth. |
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| Logic Design |
Andes Technology Adopts Cadence Digital Front-End Low-Power Flow
Andes Technology, a Taiwanese provider of high-performance, low-power 32-bit processor IP and SoC platforms, has adopted the Cadence® digital front-end low-power design flow. The flow, based on the Common Power Format (CPF), deploys Cadence synthesis, simulation and formal verification technology. It enables Andes to provide its customers a scalable and configurable low-power management framework that blends hardware and software solutions for sophisticated power domain partitions and power scaling schemes.
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Cadence and Hitachi Achieve Unparalleled Compression Efficiency to Speed Silicon Realization
The fundamental challenge in silicon realization is getting from concept to silicon quickly and cost-effectively-without sacrificing quality. To keep mutual customers ahead of the silicon and SoC manufacturing curve with higher product quality and lower development costs, Hitachi and Cadence have collaborated to deliver a top-notch test methodology that achieves 1,100x the compression efficiency of other methods. This has exceeded goals nearly 4 years ahead of industry expectations. Mutual customers now have a concurrent design-for-manufacturing optimization flow that yields first-pass silicon success.
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Reduce embedded SoC design cost & optimize IP integration
By Neil Hand, Group Director, Product Marketing at Cadence
EETimes.com, Aug 9th, 2010
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| Functional verification |
Incisive Enterprise Verifier - New datasheet available
Dual power from integrated formal analysis and simulation engines
Cadence® Incisive® Enterprise Verifier allows design teams and verification engineers to bring-up designs faster, begin bug hunting earlier in the process, gather more metrics toward verification closure by leveraging SVA and PSL covers, and reach bugs deep in the design that can be missed by a standalone simulation or formal analysis approach
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| Digital Implementation |
Archived webinar - Maximizing the Performance-Per-Watt of Your Next Design
Attend this webinar to explore the different options available to you to reduce power from both a leakage and dynamic aspect. Techniques such as multiple threshold voltage optimization and clock gating strategies will be discussed, as well as more advanced power management options such as power shutoff, multiple supply voltages, and dynamic voltage/frequency scaling. Finally, we will also explore the use of cutting-edge techniques like dual/quad flops to help you streamline your chip's performance like never before!
You will find more archived webinars about digital implementation topics that have been held recently here.
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| Manufacturability Signoff |
Manufacturing aware design flow based on early prevention, detection and fixing
At CDNLive! EMEA 2010 in Munich, NXP presented a Manufacturing Aware Design Flow based on early prevention, detection, and fixing, covering Via Doubling, Litho-, CMP-, and Variability Analysis.
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| Events |
CDNLive! Israel 2010
CDNLive! Israel 2010 is a unique opportunity to share your design challenges and successes with industry experts and other Cadence technology users. Find out the latest insights on complex design issues, solutions to address the anticipated design challenges of tomorrow, as well as practical techniques and tips from other power users and Cadence technologists to enhance your design skills.
ClubT
Join us at one of our annual "ClubT" seminars, where we will give you an update on verification solutions with Specman/e, Incisive Enterprise Simulator-XL, OVM/UVM e and multi-language UVM, SystemC, ESL/TLM, VIP, CAST, Specman-AMS and our progress on the "Trailblazer" technology roadmap.
06 Oct 2010 - Cadence Office, Feldkirchen, Germany
08 Oct 2010 - Cadence Office, Sophia-Antipolis, France
12 Oct 2010 - Novotel Grenoble Centre, Grenoble, France
14 Oct 2010 - Aztec West Bristol, United Kingdom
Allegro FPGA System Planner Technical Seminar - Oct 20, Bracknell, UK
Free half day seminar with presentations from both Altera and Cadence that include in-depth scenarios of the FPGA-PCB co-design process challenges.
TLM Design and Verification Tech Talk - Oct 27, Feldkirchen, Germany
Leveraging the experience of Cadence R&D and architects, discover the benefits of the TLM-based design and verification methodology, hear about real customer case studies, and learn how you can incrementally adopt this approach into your existing methodology.
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