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    March 2010 Issue
In this issue

Welcome to the March issue of eEuronews!

Early this year, the Accellera Verification IP (VIP) Technical Subcomittee voted to make the Open Verification Methodology (OVM) the basis of its upcoming "Universal Verification Methodology" (UVM) standard. Have a look at our Insight Industry blog and find out what this means, why it's important, and what questions will need to be answered.

To have personal conversations about this topic or any other themes that are of interest to you, mark your calendars and join us at the next CDNLive! EMEA user conference in Munich 4-6 May. Click on the picture below to watch our short video showing what attendees of last year's event had to say.

If you haven't discovered our regional Cadence EMEA website yet, and you would like to be updated on all the trainings, seminars, webinars etc in your region, please visit us here.

Our Knowledge Transfer Webinar series continues throughout March. Don't miss out on these essential technology updates. Find out more here.

Best regards,
Wolfgang Stronski
Marketing Director EMEA, Cadence Design Systems

CDNLive! EMEA 2010
In the news  
Custom Design  
Functional Verification  
Logic Design  
System Design & Verification  
Digital Implementation  
Manufacturability signoff  
PCBIC Packaging  
Education Services  
Cadence Academic Network  
Quick links

Cadence blogs

Functional Verification

Q&A: Why The e Verification Language Is Alive And Well

In spite of rumors about the decline of the e verification language, it's not only still alive but is thriving and growing, according to Mitch Weaver, corporate vice president for front-end verification at Cadence. In this interview, he answers questions about Cadence and industry support for the e language and the Specman/e verification environment, as provided by Incisive Specman Elite and Incisive Enterprise Simulator XL.


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Cadence in the news
    Les concepteurs analogiques utilisent avec succès la solution AMS Designer
    Electronique, janvier 18, 2010
    CAO-Electronique : la course entre la technologie et les outils de conception
    Industrie&, février 3, 2010

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    Knowledge Transfer Webinars

    Cadence has been hosting a series of webinars to help to increase its customers' productivity by transferring knowledge about its technologies and methodologies in key focus areas.

    Each webinar will include a 40 minute presentation, with 20 minutes for Q&A with the expert speaker. All webinars commence at 10:00am GMT on their given date. Click on one of the webinar titles to find out more or to register:

    Topic Date Speaker
    Low Power IP Integration and Macro Modelling with Common Power Format Thu 11 March John Longvill
    What's New in Allegro 16.3 PCB Editor? Tue 16 March Andrew Windscheffel
    Synthesis: The Need for Predictability Thu 18 March Bupendra Bechar
    New Layout Productivity Features in
    Virtuoso® IC6.1.4
    Tue 23 March Daniel Nelhams

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    Custom Design

    A real solution for mixed signal SoC verification By Intrinsix, an electronics design solutions company

    As more complex, mixed signal System on Chip (SoC) designs continue to stress verification methodologies and schedules, designers need new approaches in solving today's test challenges. Mixed signal verification presents a unique challenge as the analog portion of the design requires highly accurate, and time consuming, analog simulation (Spice for example).

    Read more at >>


    Things You Didn't Know About Virtuoso: Options? What Options?

    Virtuoso Layout Migrate - 614 Enhancements

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    Logic Design

    WHITE PAPER - Eliminating Routing Congestion Issues with Logic Synthesis

    The following scenario has happened to a lot of logic designers; has it happened to you? You work hard to design a chip, make sure it meets the specifications, verify it, and hand it off to be physi¬cally implemented. You go on your merry way, planning your next project, when your phone rings in the middle of the night. It is the physical implementation team telling you that your chip cannot be routed because of congestion issues. And the chip might not be able to meet either the schedule or the spec. This is every chip designer's nightmare!

    Download the White Paper >>

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    System Design & Verification

    The next IC design methodology transition is long overdue

    Anyone with a tapeout deadline looming knows how finishing a new chip design keeps getting harder and harder. Fortunately, newly standardized high-level languages like SystemC®, along with modern high-level synthesis (HLS) tools are offering designers a way to escape the RTL "productivity jailhouse". Read more at

    Q&A: How System Design And Verification Can Go "Mainstream

    System design and verification are parts of the RTL flow today, but a higher level of abstraction is now poised to enter the IC design mainstream, according to Ran Avinun, marketing group director for system design and verification at Cadence. In this interview he discusses trends in hardware/software integration, prototyping, and transaction-level modeling (TLM), and offers a perspective on the recent merger activity in the virtual platform market.


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    Digital Implementation

    Learn more about Encounter. Become a specialist.

    To experience for yourself the advantages of the new advanced digital design family, we invite you to explore all the dimensions of the new Encounter Digital Implementation System. In the process you'll be on your way to becoming a specialist in the latest requirements and techniques to address complex flat and hierarchical design closure, advanced signoff, low power, mixed signal, and advanced node design.


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    Manufacturability signoff

    Hotspot Detection and Design Recommendation Using Silicon Calibrated CMP Model

    Chemical Mechanical Polishing (CMP) has been used in the manufacturing process for copper (Cu) damascene process. It is well known that dishing and erosion occur during CMP process, and they strongly depend on metal density and line width. The inherent thickness and topography variations become an increasing concern for today's designs running through advanced process nodes (sub 65nm). Excessive thickness and topography variations can have major impacts on chip yield and performance; as such they need to be accounted for during the design stage.

    Download PDF >>

    Visit SPIE Digital library >>

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    Education Services

    Cadence Training at CDNLive! EMEA 2010
    Register now for our hands-on demo sessions or join us at the Designer Expo.

    New in our Allegro portfolio New Power Efficient Design Foundations Classes Encounter® Digital Implementation Update Training v9.1

    New in v16.3

    Contact your local training department for further information

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    Cadence Academic Network

    The Cadence Academic Network lead institutions are now listed on the Cadence website. Take a look here. More will be added soon.

    CDNLive! EMEA 2010 - Academic Track
    The CDNLive! EMEA 2010 Academic track program is full. Presentations from the lead institutions will take place on Wednesday 5th May. Other contributors to the Academic track will present on Thursday 6th May. Find out more >>

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