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  February 2010 Issue

In this issue

Welcome to the 1st edition of eEuronews in 2010!

A lot has already been said about the possible growth of chip sales in 2010 and beyond. The majority of analysts are positive and estimate that the semiconductor market will recover to the point that by the end of 2010 we could achieve similar conditions as in 2008. Given these predictions, one gladly follows the positive messages in order to replace all the less agreeable messages received last year.

An important aspect to support semiconductor market growth is to help reduce costs and improve the productivity. With the launch of the new Cadence Encounter Digital Implementation System 9.1 we launched a solution that tackles exactly these challenges. You will find more information within the newsletter below.

During the month of February and March, we will host a series of webinars in EMEA to help increase designers' productivity by transferring knowledge about technologies and methodologies in key focus areas. Have a look at the full schedule here. I hope you find the time to attend some of them.

Best regards,
Wolfgang Stronski
Marketing Director EMEA, Cadence Design Systems

In the news  
Custom Design  
Functional Verification  
Logic Design  
System Design & Verification  
Digital Implementation  
Manufacturability signoff  
PCB & IC Packaging  
Education Services  
Cadence Academic Network  

Quick links

Cadence blogs



Knowledge Transfer Webinar Series

Cadence is hosting a series of webinars to help to increase its customers' productivity by transferring knowledge about its technologies and methodologies in key focus areas.

Each webinar will include a 40 minute presentation, with 20 minutes for Q&A with the expert speaker. All webinars commence at 10:00am GMT on their given date. Click on one of the webinar titles to find out more or to register:

Topic Date Speaker
Mixed-Signal Simulation for Analog Designers Tue 23 February Marcel Ahmedzai
Understanding INCA_libs Thu 25 February Kevin Chong
Debugging Techniques for APIs and SDF Tue 2 March David Henly
Encounter® Library Characterizer - Targeting the right process corners for your designs Thu 4 March Keith Tunstall
Low Power IP Integration and Macro Modelling with Common Power Format Thu 11 March John Longvill
What's New in Allegro 16.3 PCB Editor? Tue 16 March Andrew Windscheffel
Synthesis: The Need for Predictability Thu 18 March Bupendra Bechar
New Layout Productivity Features in
Virtuoso® IC6.1.4
Tue 23 March Daniel Nelhams


Cadence news
Vers une productivité améliorée pour les concepteurs analogique
, Issue 1, 2010
Holistischer Routing-Ansatz von Cadence halbiert die Entflechtungszeit komplexer PCB-Designs
Elektronik Praxis, 01.02.2010

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Custom Design

Tips & Tricks: Things You Didn't Know About Virtuoso: Virtuoso Layout Suite - Design Rule Driven Editing (DRD) by Robert Schweiger, Field Platform Marketing, Custom IC Virtuoso

Layout Suite L provides real-time design-rule-driven editing that flags rule violations or automatically enforces design-rule correct layout. This enables correct-by-construction layout, improving productivity and reducing physical verification iterations. Advanced-node design rules, including many rules associated with 40- and 32-nanometer processes, are supported too. So DRD increases not only the productivity but also helps you to improve the design quality ensuring process design-rule correctness in real-time.

If you would like to find out more on DRD then simply watch a short video and learn how you can enable and use the design rule driven editing mode in the Cadence Virtuoso Layout Editor. To watch the video, click here.

BTW: If you would like to see more videos then simply log in to SourceLink and have a look into our video library by browsing Support Home > Resources > Video Library

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Functional Verification

Cadence OVM SystemVerilog Solution Enables More Thorough Verification and Reduces Costs at Mitsubishi Electric

Company Cites 40% Reuse Leading to Lower Costs, Better Quality

Mitsubishi Electric Corp. has adopted Cadence® verification technology, including a unique adaptation of the Open Verification Methodology (OVM), that has helped cut verification time and improve ASIC product quality. By deploying the Cadence OVM SystemVerilog module-based solution, Mitsubishi has been able to conduct more thorough verification on its chips while reducing costs.

"This methodology has enabled us to reuse 40 percent of our verification components throughout a series of ASIC developments," said Yoshimasa Ishino, department manager, LSI Design Engineering Department at Mitsubishi Electric Corporation's Design Systems Engineering Center. "Building and reusing verification components based on OVM makes it easier to focus on the enhancements introduced in the new products. As a result, we were able to reuse our previous verification environment and reduce the time it took us to complete the new environment by 30 percent. We are sure that the Cadence OVM SystemVerilog module-based approach will be an effective way to reduce our resources and costs used for SystemVerilog-based verification."


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Logic Design

CADENCE BLOG - RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition!

In recent months there have been calls for a re-tooling of the RTL-to-GDSII flow. The argument was that for designs 20M gates or larger, you needed to synthesize at the chip-level, and synthesize in conjunction with placement. There are also verification problem of chips this size. This blog posting looks at this issue and wonders if there are more radical solutions.


EDADESIGNLINE.COM GUEST BLOG: Lowering test costs in the nanometer era

Design for test (DFT) has not drawn the kind of attention that design for manufacturability (DFM) has received in recent years, but test is becoming significantly more difficult and expensive at nanometer process nodes. Test costs are escalating, adding to overall product costs, and the potential for yield loss due to test-related issues is rising. What's needed is a renewed focus on DFT with a more holistic view of the economics of test than we've had in the past. 

Read more of this blog by Sanjiv Taneja at >>

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System Design & Verification

Cadence Helps Casio Maintain its Lead in Digital Cameras

Casio breaks productivity barriers using new TLM-driven design and verification In 1995, Casio Computer Co., Ltd., developed a digital camera with an LCD display, paving the way for the digital camera of today. The Casio EXILIM, originally launched in 2002, has been well-received for a broad range of sizes, performance, and price points. All are renowned for their ability to shoot images in rapid sequence, with sharp resolution, high-contrast, and true-to-life colors. EXILIM cameras also deliver long battery life.

These capabilities result from the powerful and power-efficient image processing functions performed in the EXILIM camera System LSIs. These SoCs-which typically have millions gates-perform most of the image capture and processing functions within the camera. The engineers at Casio's Digital Camera Division are responsible for developing these advanced SoCs and are world-class experts with deep experience in algorithm development and architectures for digital cameras.


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Digital Implementation

New Encounter Digital Implementation System enables superior design productivity and quality

Relentless consumer demand for the next big thing-in ever smaller form factors-is putting semiconductor makers in a bind. They must create chips with unprecedented functionality, while dealing with conflicting design goals such as ultra-high performance and low power. The resulting scale and complexity of these chips leads to productivity issues, design schedule delays, and silicon yield challenges. Recognizing these hurdles facing digital designers, Cadence has focused a major R&D effort on developing innovative and robust EDA tools that deliver significant improvements in productivity, predictability and quality. One result is the newest version of the Cadence® Encounter® Digital Implementation (EDI) System.

Learn more >>

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Manufacturability signoff

Convergent Automated Chip Level Lithography Checking and Fixing at 45nm

To provide fabless designers the same advantage as Integrated Device Manufacturer (IDMs), a design-oriented litho model has been calibrated and an automated lithography (litho) hotspot detection and fixing flow has been implemented during final routing optimization. This paper shows how a design-oriented litho model was built and used to automate a litho hotspot fixing design flow. The model, calibrated and validated against post-OPC contour data at 99%, was embedded into a Litho Physical Analyzer (LPA) tech file. It allowed the litho contour of drawn layouts to be simulated at full chip level to detect litho hotspots and to provide fixing guidelines. Automated hotspots fixing was hence made possible by feeding the guidelines to the fixing tools in an industry based integrated flow. Post-fixing incremental checks were also performed to converge to a clean design.

Download PDF >>

Visit SPIE Digital library >>

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PCB & IC Packaging

Cadence Allegro and OrCAD 16.3 Release
Virtual Conference on-line now

Take advantage of all the recorded presentations provided by our strategic partners and industry experts. You'll have convenient access to the keynotes in a virtual conference hall and you can explore 7 booths of interest within a virtual exhibition hall. Register here for a full replay of the conference!

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Education Services
Advance for Engineer Explorer Series - our portfolio for expert knowledge
AMS Simulation Analog Simulation Physical Design
Behavioral Modeling with Verilog-AMS RF Analysis with Virtuoso Spectre Simulator Virtuoso Floorplanner-vIC6.1.3
SystemC SystemVerilog Specman
Transaction Level Modeling V2.0 (TLM) SystemVerilog Advanced Verification using OVM Specman Elite Advanced Verification-v9.2
Formal Verification Power Analysis High-Speed
Advanced Logic Equivalence Checking with Encounter Conformal EC Signoff Power-Grid Analysis with Encounter Power System

Advanced Signoff Power-Grid Analysis with Encounter Power System

Allegro High-Speed Constraint Management v16.3

Download our latest training catalog and schedule. To receive a paper copy, please contact your local training representative.

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