Back to School with
Encounter Digital Implementation System v8.1

Date & location:
September 10th 2009 - Institut für Elektrische und Optische Nachrichtentechnik Universität Stuttgart

The Cadence® Encounter® Digital Implementation System delivers new foundational ultra-efficient core memory architecture for the ultimate in capacity and performance along with the industry's first and only native and truly scalable end-to-end multi-core design backplane. It also provides a completely extensible architecture to handle the latest requirements for design closure, low power, mixed-signal, design for manufacturability, and yield optimization for complex, advanced node flat and hierarchical designs.

Attend this seminar and get a glimpse of the Encounter Digital Implementation System in person and discuss its capabilities with Cadence technologists.

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What you will see

During this highly technical series, you will hear presentations that include in-depth scenarios of digital design challenges that you may be struggling with today, as well as the latest features and functionalities of the Encounter Digital Implementation System that will help you overcome such challenges. In addition, you will see technology demonstrations in each of the five areas where the Encounter Digital Implementation System excels: design closure, low power, mixed signal, signoff analysis, and advanced node, including new 32nm requirements.

Don't miss this opportunity to interact with other users, new users, and technical experts. Find out how to:

• Develop automated, multi-dimensional floorplans for fast design closure
• Accelerate design runtimes with a timing-convergent design flow
• Save design power using multiple techniques, a hierarchical flow, the right number of power-switches and a simple solution for always-on buffers
• Get early feedback on the power grid for IR drop and rush current
• Pick the correct chip package early on in the design flow with a right balance of decoupling capacitors
• Manage floorplan/timing/ECOs between analog and digital design teams
• Analyze substrate noise and impact on analog IP
• Support requirements for 32nm, DFM, and DFY
• Push design performance and power limits with a comprehensive methodology for systematic and random variation
• Sign-off at top-level and handle multiple modes/corners without adverse runtime and memory impact

Who should attend?

• Digital design engineers and engineering managers designing chips in the digital domain
• Anyone looking to interact with technologists and fellow digital designers

Agenda

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September 10th 2009 - Institut für Elektrische und Optische Nachrichtentechnik Universität Stuttgart

Full location details:
Institut für Elektrische und Optische Nachrichtentechnik
Universität Stuttgart
Pfaffenwaldring 47
70569 Stuttgart
Germany
On site organizer: Martin Schmidt, +49-(0)711 685 67920