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July/August 2010 Issue
 In this issue
In the news
System Design and Verification
Functional Verification
Logic Design
Custom IC
Manufacturability Sign-Off
Digital Implementation
Education
Events
PCB Design
 Quick links
Cadence blogs
Events
EDA360The way forward for electronic design
Twitter
Welcome to the July/August issue of eEuronews!

Each year, Cadence EMEA issues a combined Jul/Aug summer edition of eEuronews. The next issue of eEuronews will be in your inbox at the beginning of September, following the summer holidays.

To keep you updated on the latest design topics in the meantime, Cadence also offers a series of recorded webinars you can view at your convenience. Once you have signed up via the Cadence Support Home page, you'll find the Video Library with a variety of topics under Resources. Have a look at the Custom IC section below for a link to one of our recommended webinars.

If you want to get more familiar with the latest perspectives on EDA360, listen to the DAC attendee interviews that were recorded last month. On our dedicated microsite you will also find the latest video from Cadence explaining the industry vision for EDA360 in a nutshell.

Please don't hesitate to share this newsletter with your colleagues. Our goal is to deliver news that is relevant to the EMEA region - especially when it comes to events and webinars - and share the latest product updates, interesting articles, and blog posts with you.

Best regards, and speak to you again in September!

Wolfgang Stronski
EMEA Marketing Director at Cadence

 Cadence in the news
Cadence Completes Acquisition of Denali »

Cadence Global Services Enables Industry's First TD-LTE Baseband Chip from Innofidei »

SiS Adopts Cadence Technologies for Advanced SoC Designs »

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 System Design and Verification
What Language Is Best For High Level Synthesis?
Blog by Richard Goering, Cadence

Richard Goering attended a DAC panel entitled: "What input language is best for high-level synthesis?" The panel comes at a time when most high-level synthesis (HLS) providers, like Cadence, have embraced SystemC. Mentor Graphics is the most recent addition to the list. But not all HLS tools take SystemC. Synopsys (not on the panel) introduced synthesis from Matlab/Simulink earlier this year. Bluespec (on the panel and very vocal) provides synthesis from SystemVerilog. The panel included some pointed debates between Rishiyur Nikhil of Bluespec and most of the other panelists.

Read More »

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 Functional Verification
Why The UVM Is Ready For Production Use Today
Blog by Tom Anderson, Cadence

Read about Tom Anderson's trip to DAC where he spent the largest percentage of his time at the OVM-UVM booth, educating attendees on the status of the Universal Verification Methodology (UVM) and answering their questions. Many people had heard about the UVM, although some were unclear on its relation to the Open Verification Methodology (OVM) but Tom emphasized the tight link between them.

Read More »

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 Logic Design
Now Available: Encounter RTL Compiler 10.1
Blog by Jack Erickson, Cadence

The latest major release of Encounter® RTL Compiler is available for download (look for "RC101"). Some of the highlights include:

• Quality of Silicon improvements
• Multi-vt algorithm improvements
• Runtime improvements for large designs
• Floorplan tweaking
• Rapid re-synthesis
• Superthreading no longer requires GXL
• DFT

Read More »

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 Custom IC
Tips & Tricks: Things You Didn't Know About Virtuoso: Constraint Driven Flow in Virtuoso IC 6.1.4
By Robert Schweiger, Field Platform Marketing, Custom IC

Since the first release of Virtuoso IC 6.1 back in October 2006 we've been supporting a constraint-driven design flow. As customers are adding more and more constraints an automated mechanism was needed to automatically verify them inside Virtuoso. In Virtuoso IC 6.1.4 we've added now a constraint checker" to verify all constraints in the design and visualize their status in the constraint manager. By verifying the constraints designers can ensure that all constraints in the design are applied and met.

Recently we've created a video that demonstrates the Constraint Driven Flow in IC 6.1.4. It shows how design requirements can be captured and transferred using the Constraint System and how the constraints are implemented and verified in the Layout by automatic or interactive tools.

If you would like to find out more on the Constraint Driven Flow then simply watch a short video and learn how you can leverage constraints in your design. Click here to watch the video

BTW: If you would like to see more videos then simply log in to the Cadence Online System and have a look into our video library by browsing Support Home > Resources > Video Library

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 Manufacturability Sign-Off
Modeling stress-induced variability optimizes IC timing performance

Many design teams migrate to advanced IC process nodes to increase performance while reducing area and power. Timing performance and predictability can be compromised, however, if there's too much systematic variability. Fortunately, systematic variability can be modeled and mitigated if one understands the causes. A leading cause of systematic variability at 45nm and below is the application of mechanical stress to transistors.

Learn More »

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 Digital Implementation
Silicon Realization Enables Next-Generation IC Design

Silicon Realization represents a new way of looking at an old challenge-the design and verification of ever-more complex intellectual property (IP) blocks, ICs, or systems-on-chip (SoCs).

Part of the larger EDA360 vision, Silicon Realization brings fresh perspectives to such challenges as digital verification, mixed-signal implementation and verification, low-power design, advanced process nodes, IC/package co-design, and giga-gate, gigahertz complexity. Silicon Realization promises integrated and interoperable flows that allow concurrent, objective optimization for function, performance, power, unit cost, and other design requirements.

Learn More »

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 Education
Virtual classroom (VC) trainings:

- Live trainings without travel time and costs!

14th-17th September 2010: Encounter RTL Compiler

4th-7th October 2010: SKILL Development of Parameterized Cells

Contact us for further details or click here.


Training highlights:

• SystemVerilog Assertions completely revised to utilise the most effective use models - learn more

• All new SystemC Synthesis using C-to-Silicon Compiler training

Allegro 15.7 to 16.3 Update

• Specman Elite Basics for Verification Environment Users / Developers

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 Events
2010 Technology Updates for Encounter Digital Implementation System and Cadence Logic Design Solution
During this highly technical series, you will hear presentations that include in-depth scenarios of digital design challenges that you may be struggling with today, as well as the latest features and functionalities of the Encounter Digital Implementation System and the Cadence Logic Design Solution that will help you overcome such challenges.


PCI Express 3.0 Advanced Verification Webinar
This webinar will review the verification challenges of PCI Express devices and will outline the principles and techniques of a metric-driven methodology for exhaustive pre-silicon functional verification using concrete application examples of the latest PCIe 3.0 protocol features.


"Electronical" Co-Design between Allegro PCB Design and PTC Pro-Engineer
Many companies are incorporating sophisticated high-density electronics within more complex mechanical enclosures such as portable consumer electronics and automotive and medical devices. To design these products successfully, companies need to break down the organizational, technical, and methodology barriers that have traditionally limited design collaboration across different disciplines. Learn how to implement an ECAD/MCAD co-design methodology to enable a co-design process, bi-directional communication, and collaboration between the PCB and the enclosure design teams.


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 PCB Design
What's Good About Via DRCs In Allegro Constraint Manager? It's In SPB16.3!
By Gerald "Jerry" Grzenia, Cadence

Current design technologies require extremely tight matching requirements right down to the overall net topologies to ensure that any deviations in propagation delays are minimized. As a result, design guidelines call for matching the number of vias for a group of signals.


What's Good About Vias And The Allegro Router? SPB16.3 Has A Few New Enhancements!
By Gerald "Jerry" Grzenia, Cadence

A few new enhancements specific to vias in the SPB16.3 release of Allegro PCB Editor have been introduced. The are called use via region and stacked via support.

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