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June 2011 Issue
 In this issue
In the News
System Design and Verification
Logic Design
Functional Verification
SoC Realization
Custom IC Design
Manufacturability Signoff
PCB and SiP design, IC packaging
Academic Network
Education Services
 Quick links
Cadence blogs
Events
Twitter
Welcome to the June issue of eEuronews!

From June 5-9, the Design Automation Conference (DAC) took place in San Diego, California. During the conference, customers presented quantified results and successes they have enjoyed using Cadence® technology, products, and solutions. You will find a great number of blogs on our community website that describe various demos, sessions, and discussions from the event.

I also would like to redirect you to the CDNLive! EMEA Multimedia Channel. In the last weeks, we added new videos from our customers that presented papers at the user conference. The conference proceedings are now available for download. Use your cadence.com user account to log in. The next CDNLive! will take place in Tel Aviv, Israel, September 26, 2011.

If you find the content of this newsletter useful to you, please don't hesitate to share it with your colleagues.

Best regards,

Wolfgang Stronski
Marketing Director EMEA, Cadence

 News
Cadence Focuses Industry on 20-nm Chip Design at Design Automation Conference »

Cadence Extends IP Offering, Collaborates with TSMC via Open Innovation Platform »

Cadence Collaborates with TSMC on New 28-nanometer Flows »

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 System Design and Verification
A Closer Look at the Cadence Virtual System Platform - Q&A with Steve Brown

Cadence took a significant step into a new marketplace with the recent introduction of the Virtual System Platform, a virtual prototyping environment that supports architectural-level, pre-RTL software development and debugging. The Virtual System Platform is part of the tightly integrated System Development Suite, which also includes testbench simulation, RTL acceleration/emulation, and FPGA-based prototyping.

In this interview Steve Brown, product management director at Cadence, talks about the limitations and challenges of virtual prototyping today and discusses some of the capabilities provided by the Virtual System Platform.

Read more »

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 Logic Design
Imec and Cadence Deliver Automated Solution for Testing 3D Stacked ICs

Imec and Cadence have announced new technology that delivers an automated test solution for design teams deploying 3D stacked ICs (3D-ICs). The technology addresses the test challenges involved as electronics companies increasingly turn to 3D-ICs as a way to increase circuit density and achieve better performance at lower power dissipation for mobile and other applications where space is at a premium.

This imec-Cadence collaboration provides the design-for-test (DFT) and automatic test pattern generation (ATPG) technology that will make it easier to test 3D-ICs with "through-silicon via" (TSV) functionality and help ensure that the stacked system will work as intended.

Read More »

Erik Jan Marinissen, imec - CDNLive! EMEA 2011 Paper Presentation Summary

Erik Jan Marinissen, imec, a presenter at CDNLive! EMEA 2011, discusses the "Implementation Aspects of a 3D DFT Architecture".

View video »

For more CDNLive! EMEA 2011 customer videos, visit our multimedia channel

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 Functional Verification
Cadence Accelerates Development of Multiprocessor Mobile Devices with New ARM ACE Verification IP

Cadence has announced the immediate availability of verification IP (VIP) for ARM Ltd.'s new AMBA 4 Coherency Extensions protocol (ACE), extending its popular VIP catalog and speeding the development of multiprocessor mobile devices. The new VIP enables designers to verify the functionality of multiprocessor ARM Cortex®-A15 designs now being deployed in a variety of mobile applications including consumer tablets and smart phones.

"Mobile design complexity has grown to the point that it requires capabilities previously only found in very high-performance systems," said Michael Dimelow, Director of Marketing, Processor Division, ARM.

Read More »

Functional Verification Webinar Series
June 23, 2011 - at your Desktop: 7:00PM - 8.00PM CET (Central European Time)

Register modeling is critical for IP and SoC verification, as a large part of the stimulus relies on configurable modes and activation of these modes at all levels. This webinar comprehensively covers this subject and shows you how it's done-from design to debug, execution to error handling.

More Information »

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 SoC Realization
Achieve your SoC Design Goals - Measure Twice, Cut Once!
EETimes.com
By Dr. Anis Uzzaman and Kenneth Chang, Cadence

Every new SoC design starts with "The Idea" (for the purposes of this paper we will take the term SoC to embrace ASICs and ASSPs). In some cases someone essentially says "We need to create a new device that does this, that, and the other; an incredible design that will be far better than anything else out there; and one that will bring us a lot of money while making our competitors rue the day that they didn't think of this first!"

Of course, not all new chips are of the "wiz-bang let's change-the-world" variety. Many are customer driven derivatives of something that already exists, with very tight market and cost windows, but these designs also start life as an idea in someone's head.

Read More »

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 Custom IC Design
Jim Hogan Presents Vision of "Democratized" MEMS

If you work with micro-electrical mechanical systems (MEMS) today, you are probably a highly trained expert. And that's a problem. For MEMS devices to become more prolific in consumer devices, we need to "democratize" MEMS design and integration so it's not confined to a handful of PhD-level experts working in IDMs on projects that take four years to complete.

That's the message that EDA investor Jim Hogan brought to a Cadence/Coventor seminar held May 18 at Cadence San Jose headquarters. Coventor is a provider of MEMS design and simulation tools, and its MEMS+ offering, which facilitates MEMS integration into ICs, works closely with the Cadence Virtuoso platform. The one-day seminar provided a hands-on demonstration of that connection, as well as keynote speeches by Hogan and by Steve Breit, Coventor vice president of engineering.

Diagram

Read blog »


Webinar: June 28, 2011 - at your Desktop : 6:00 PM - 7:00 PM CET (Central European Time)

Cadence and IC Manage - IP Reuse and Parasitic-Aware Design Using Cadence Virtuoso Technologies and the IC Manage Global Design Platform

Technology experts from IC Manage and Cadence present the advancements in the area of custom IC design and verification, focusing on IP collaboration/reuse and parasitic-aware design.

More information »

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 Manufacturability Signoff
DFM - Buy Tools or Hire Services? Cadence Offers Both for TSMC

If you're planning a 40nm or 28nm design with TSMC, you have two options for meeting design for manufacturability (DFM) requirements -- either buy EDA tools and run DFM checks, or turn to a services provider to run them for you. On May 9, Cadence became the first EDA partner to be certified by TSMC for DFM services, including lithography process checks (LPC) and chemical mechanical polishing (CMP) checks. Here's some background on how that happened and what that means.

Read blog »
Cadence DFM Services
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 PCB and SiP design, IC packaging
VeriSilicon and Cadence Collaborate on a a Flexible and Robust Prototyping Platform for Hardware/Software Integration and Co-verification

VeriSilicon provides custom silicon solutions that require its engineering team to combine digital signal processing cores, embedded memory, and mixed-signal intellectual property into system-on-chip (SoC) platforms that are used in consumer electronics devices.

When VeriSilicon started working on a custom design that utilizes four FPGAs, they had an aggressive timeline and no room for error. They needed a flexible and robust prototyping platform for hardware/software integration and co-verification.

Find out how Cadence Allegro FPGA System Planner XL helped the VeriSilicon team complete pin assignment in just one week with an automated, placement-aware approach.

Download success story »

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 Academic Network
Prof. Mladen Berekovic on CDNLive! EMEA 2011 in Munich

Mladen Berekovic, Professor for VLSI Design, University of Jena, discusses the Cadence Academic Network, its initiatives and impacts, while attending CDNLive! EMEA 2011.

Screenshot

View video »

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 Education Services
July to December 2011 - dates now released

Please have a look at our website to check for specific dates or contact your local training contact to receive your personal schedule.

New Additions to our training portfolio:

Please check our website or contact your local training contact for further details.

Acceleration and Emulation Using Palladium XP v1.0 »
Topics covered include preparing a design for emulation or acceleration, improving simulation acceleration performance, creating synthesizable testbenches, an introduction to transaction-based acceleration, design debugging using Palladium XP, running dynamic power analysis using Palladium XP, and analyzing power shutoff systems using CPF (Common Power Format).

Physical Verification System v10.1 »
Users will learn how to use the powerful and straightforward PVS debugging environment to locate errors and fix real problems quickly.

SystemVerilog Advanced Verification using UVM 1.0 »
Our UVM training delivers both a description of UVM and an effective, proven methodology for it's use. UVM lab exercises are based on the verification of a real-life router design, from data description through UVC creation to multi-UVC integration, coverage and scoreboarding.

New in Virtuoso 6.1.5

Virtuoso Analog Design Environment v IC6.1.5
Virtuoso Schematic Editor vIC.6.1.5
Virtuoso Spectre Circuit Simulator vMMSIM 10.1

New Virtual Classes - New Classes and Dates Available

Virtual Classroom is a web-based environment that allows you to participate in live training events without the need to travel. You listen to lectures, participate in lab exercises, ask questions, and receive feedback just as you would do in a conventional classroom. It saves the hassle, expense, and travel time to a training site.

Have a look at our complete offering --> select view: "Virtual Class" Select view: Virtual Class

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