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September 2012 Issue
 In this issue
Cadence News
Cadence Events
Custom IC Design
Digital Implementation
Logic Design
Functional Verification
System Design and Verification
Low Power
Manufacturability Signoff
IP News
PCB
Education Services
twitter
Welcome to the September/October edition of eEuronews!

Have you seen the iPhone5 announcement? Isn't it absolutely amazing how much computing power you can have in your pocket these days for an affordable price and with an acceptable battery lifetime?

This is thanks to you all! You, the semiconductor and systems engineers, who manage to develop more and more complex semiconductor and system products under ever increasing constraints in terms of performance, power, area (PPA), process complexity and time-to-market requirements.

The mobile computing and smartphone market is definitively a key driving force for the adoption of the latest technology nodes. 20nm will enable a new generation of smaller, faster, more differentiated products with a chip complexity of up to 8-12 billion transistors. Even if you are not currently considering 20nm design, please download and read a new 9-page White Paper titled "A Call to Action: How 20nm Will Change IC Design" to learn about some fundamental shifts in the ways these new chips are being designed and fabricated.

Having said that, did you know that an estimated 70% of all design starts worldwide are mixed-signal designs and 93% of those mixed-Signal designs are at 65nm or above?

Mixed-signal applications are one of the fastest growing market segments in the semiconductor industry and particularly relevant to us in EMEA. The analog complexity, the digital content and the complexity of the embedded processors integrated are increasing rapidly. In order to ensure the desired quality of results, a holistic mixed-signal methodology is required for design, verification and implementation of state of the art mixed-signal ICs.

Mixed-Signal Methodologies book cover

Therefore, Cadence published a book about 'Advanced Mixed-Signal Methodologies' in mid-August. It is the EDA industry's first comprehensive review of the advanced design, verification, and implementation techniques required to successfully develop today's analog/mixed-signal IP, IC, and SoC designs. You can order and get a free preview of the first chapter of the book here.
Also, please view our Technology on Tour events which we conduct across Europe in October.

Another amazing growth area in microelectronics lies in automotive electronics. The dollar value of electronics in automotive has tripled over the last decade and the amount of software code increased by a factor of 100! Automotive designs are typically mixed-signal embedded system designs, which have to fulfill stringent reliability, safety and security requirements.
 
In August, we launched the first thesis contest for automotive embedded systems. The deadline for the final paper is Sept 28. If you know any Diploma, Bachelor, and Master contestants please forward the following link that contains all the instructions: http://www.cadence.com/cadence/events/Pages/designcontest2012.aspx
The winners will be announced at the next CDNLive! EMEA, taking place in Munich from May 6-8, 2013.

In order to help you designing reliable electronic systems with high speed interconnects, Cadence is expanding its Design IP portfolio with industry leading, silicon proven 28nm DDR4 and PCI Express IP Solutions. Moreover, in order to help you verify the integrity of your high speed signals in such a complex system, Cadence acquired Sigrity, a leader in High-Speed PCB and IC Packaging Analysis tool and integrated  the Sigrity analysis technologies with Cadence's Allegro® and OrCAD® design tools to provide a front to back solution to our customers. More information is available here.

It is an exciting time to be in the semiconductor and microelectronics industry! Don't you think?

Best regards,
Christian Malter
Director Technology Solutions, EMEA


 Cadence News
Cadence Acquires Sigrity, a Leader in High-Speed PCB and IC Packaging Analysis »

Denso Gains Significant Productivity and Quality-of-Results Advantages with Cadence Mixed-Signal, Low-Power Solutions »

Cadence and the National Research University of Electronic Technology (MIET) Celebrate 10 Years of a Successful Master's Degree Program »

ARM and Cadence Collaborate to Optimize ARM POP Solutions with Cadence Encounter Digital Platform »

Cadence Launches Thesis Contest For Automotive Embedded Systems »

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 Cadence Events

Technology on Tour: Mixed-Signal Seminar, Oct 15-25, 2013, various locations in UK, DE, FR, NL
Mixed-signal applications are one of the fastest growing market segments in the electronics and semiconductor industries. Join us for a free full-day technical seminar! You'll learn best practices and gain valuable insight from Cadence® mixed-signal R&D experts at a location near you!

Registration and agenda »

Technology on Tour: Club T Seminar, Munich, Germany, Oct 16, 2012
Cadence invites you to our free, one-day ClubT seminar.
We will provide you an update on our verification solutions with Specman/e, Incisive Enterprise Simulator-XL, UVM e, Debug Analyzer, VIP, UVM-e Low Power, and our progress on the "Trailblazer" technology roadmaps.

Registration and agenda »

2nd Half Functional Verification Webinar Series
Join Cadence® verification experts for a series of technical webinars on the most relevant topics in functional verification. We'll introduce you to the latest techniques, best practices, methodologies, and support services you need for developing and verifying your silicon designs-productively and profitably!

Registration, dates and topics »

SAME 2012, Sophia Antipolis, France - Oct 2-3, 2012

Visit Cadence in booth #11 and attend special speaking sessions on Advanced Design Methodologies. Francois Lemery /ST will present the Cadence/ST 20nm flow based on layout dependent effect extraction and simulation of automatically generated analog and custom layout on Oct 3 at 13:30 - 15:00 in the Session Advanced Design Methodologies.

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 Custom IC Design

How real number modelling is easing the analogue simulation challenge
Article based on interview with Tom Beckley and John Pierce from Cadence
New Electronics

The world of electronics brings some interesting conflicts, perhaps none more interesting than the stark contrast between the analogue and digital domains. The technologies are different, the design engineers are different and the ways in which designs are verified are different.

Read article »

SKILL for the Skilled: Many Ways to Sum a List (Part 2)
Blog by Jim Newton, Cadence

In the previous posting, SKILL for the Skilled: Many Ways to Sum a List (Part 1), I showed a couple of ways to arithmetically sum up a given list of numbers. In particular, I was presenting the following function definition.
(defun sumlist_1b (numbers)
(apply plus numbers))
In this posting, (Part 2), we'll look at improving this implementation by using the apply function with more than two arguments to enable handling of short lists.

Read blog »

Things You Didn't Know About Virtuoso: The (Setup) State of Things
By Stacy Whiteman, Cadence 

I last left you with an article about how to parameterize and manipulate device properties in your design without having to edit the schematic. So there you are -- creating and matching and ratioing parameters willy-nilly.  You've changed values and defined ranges and run sweeps. 
And now you're wondering--how in the world can I keep track of all this information?  How do I re-use a particularly good set of parameter values that I found during a sweep or optimization and run a Monte Carlo or Sensitivity Analysis on it or simulate it over corners?  And while we're on the subject, I need different simulation settings when I run Monte Carlo as opposed to sweeps and corners.  It's a pain to have to do all this hand-editing or reload old simulation history items to switch back and forth.  What if I make a mistake?

Read blog »


Angelo Consoli

Angelo Consoli, Managing Director at Saphyrion, details how they leverage the Cadence Virtuoso custom/analog flow and design services to develop ASICs High-End ground and space applications.

View video »   YouTube

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 Digital Implementation

In-Design Signoff Avoids Iterations and Accelerates Time to Tapeout
By Peter McCrorie, Cadence - Chip Design. com

If you look back at the history of signoff in EDA, you will find that signoff originated as a final standalone sanity check to make sure that a design was ready to be delivered to manufacturing. In the earliest of days, this was focused on design rule checking (DRC) and layout vs. schematic checking (LVS), but as process technologies shrank, and designs got more complex and the requirements for signoff expanded. Today's signoff includes timing and signal integrity (SI) for ASIC designs, power analysis (IR drop and electro migration), and design for manufacturability (DFM) analysis to ensure that lithography and chemical mechanical polishing (CMP) effects aren't going to cause yield issues.

Read article »

In Case You Missed It - The Most Popular EDI System Knowledge Content Published in Recent Months
Blog by Brian Wallace, Cadence

I mentioned in my first blog one of my roles in customer support is to identify and author knowledge content for Cadence Online Support (http://support.cadence.com). In this blog post I want to highlight some of the popular Encounter Design Implementation (EDI) System content published in recent months.

Read blog »

Why Multi-Mode, Multi-Corner (MMMC) ECO Closure Requires a New Signoff Approach
By Richard Goering

In the semiconductor design flow, engineering change orders (ECOs) are as inevitable as death and taxes. While this has always been the case, ECO timing closure is becoming increasingly difficult as the number of operating modes and process-voltage- temperature (PVT) corners skyrockets. What's needed is a new "physically aware" MMMC ECO timing closure flow.

Read blog »

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 Logic Design

Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)
Blog by Sumeet Aggarwal, Cadence

A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis, Test and Verification Flow were born! What is a RAK?

Read blog »

Tips for Fixing Timing Violations and Adopting Best Practices for Optimization with RTL Compiler
Blog by Sumeet Aggarwal, Cadence

Best Practices for Optimization:
What should be my considerations while preparing data? Libraries, HDL, Constraints...
A good result from a synthesis tool depends greatly on the input data. An old saying "garbage in garbage out" is also true for RTL Compiler. Before attempting to run synthesis, the user should check the input data, pay attention to the warning messages and correct any obvious issues.
How do I set and achieve my optimization goals?

Read blog »

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 Functional Verification

STMicroelectronics

Download success story »

IBM Relies on Cadence to Speed Distributed Teams' Verification Management
For IBM, the biggest challenge facing BIST verification teams isn't architecting or debugging the environment. It's generating weekly status reports to ensure focus on critical areas. The overload of project information typically leaves too many people spending too much time creating reports. To speed things up, IBM turned to Cadence® Incisive® Enterprise Manager.

View video »

What Does it Take to Migrate from e to UVMe?
By Team Specman

So you are developing your verification environment in e, and like everyone else, you've been hearing a lot of buzz surrounding UVM (Universal Verification Methodology). Maybe you would also like to give it a try. The first question that pops in your mind is, "What would it take to migrate from e to UVM e?"

Read blog »

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 System Design and Verification
The Seven Layers Of Hardware-Software Debug - Frank Schirrmeister, Cadence
Chip Design Magazine.com/system-level-design community

This post is about hardware/software debug, and I tried to layer a set of different levels for the scope and applicability of debug. I counted seven layers, but I am sure that one may be able to arrive at a different numbers of layers of debug depending on one's counting.
The layers I counted are illustrated in the graphic associated with this post. It shows a multi-core chip as it could be used as an application processor for phones or tables. The chip features multiple processor cores - including ARM big.LITTLE - and features customer specific blocks for graphics and application acceleration, high-speed, low-speed and general peripherals.

Read More »

Introduction to the Linux Kernel Message System
Blog by Jason Andrews, Cadence  

One of the most common problem reports related to Virtual Platforms running Linux goes something like:
I run the simulation and the terminal says "Uncompressing Linux... done, booting the kernel" and nothing happens.
One of my favorite books is Embedded Linux Primer: A Practical Real-World Approach (2nd Edition) by Chris Hallinan. I was happy to see this same situation also occurs on real boards running Linux, and it is covered in Chapter 14 with a section called "When It Doesn't Boot".

Read blog »

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 Low Power

The evolution of power formats standards: A Cadence viewpoint

Si2's contribution of the Open Low-Power Methodology (OpenLPM) to IEEE, in 2011 marked an important milestone in the development of power format standards for the industry. Cadence, among many other industry leaders, supports this contribution-it shows the most promising path for the industry to converge on one power format standard. Methodology convergence, however, is a pre-requisite for future power format convergence. This paper explains what methodology convergence is; why the OpenLPM is a promising step toward power format convergence; and how Cadence technologies can help customers develop low-power designs successfully while the industry is progressing along the path to convergence.

View White Paper »

RAK: Conformal Low Power Advanced Features for Power Intent Comparison, Hierarchical Integration and CPF Macro Modeling
Blog by By Sumeet Aggarwal, Cadence

Why do you define macro models? Luke Lang, Engineering Director at Cadence, says that "Just because you have a hard macro doesn't mean you need to define a macro model: A single-domain hard macro without any low power component should be black-boxed. A macro model is not necessary."

Luke further elaborates: "Custom IP blocks and analog macros often contain low-power features. A pure black box makes verification and implementation almost impossible. So, you need macro modeling as it provides the necessary power information to enable verification and implementation." The diagram below depicts Common Power Format (CPF) macro models.

Read blog »

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 Manufacturability Signoff

20nm design: What have we learned so far?
EDA360 Insider - Blog by Steve Leibson

Even if you are not currently considering 20nm design, you owe it to yourself to download and read a new 9-page White Paper titled "A Call to Action: How 20nm Will Change IC Design" to learn about some tectonic shifts in the ways these new chips are being designed and fabricated. Early indications point to a 30-50% performance gain, 30% dynamic power savings, and 50% area reduction for 20nm chips compared to 28nm. Chip complexity may range up to 8-12 billion transistors. Consequently, the 20nm node will be compelling for many applications that demand the pinnacle of IC density, power, and cost. This is especially true in the consumer space. With its power, performance and area (PPA) gains, 20nm will enable a new generation of smaller, faster, more differentiated products in markets such as mobile computing, smartphones, servers, entertainment, and wireless equipment. Because of these advantages, the adoption of 20nm process technology is inevitable because...

Read blog »

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 IP News

Cadence Announces Industry's First DDR4 Design IP Solutions Are Now Proven in 28nm Silicon

Cadence announced that the first products in the Cadence DDR4 SDRAM PHY and memory controller design intellectual property (IP) family have been proven in silicon on TSMC's 28HPM and 28HP process technologies.
Extending its leadership in advanced DRAM interface IP technology, Cadence has received and characterized multiple versions of its DDR PHY and controller IP in 28nm silicon based on advanced drafts of the DDR4 standard.

Read press release »

Cadence Adds Powerful New Capabilities to Its PCI Express Verification IP Including PIPE4 Support

Cadence announced powerful new capabilities in its PCI Express® Verification IP (PCIe® VIP) which result in more in-depth verification of the most current PCI Express specification at both the block and system-on-chip (SoC) levels.

Read press release »

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 PCB

IC Package prototyping methodology estimates feasibility and cost - By Tom Whipple, Cadence - EETimes

Prototyping makes it possible to explore a number of technology and architectural alternatives, and to find the most cost-effective solution that meets systems requirements. 

Read article »

What's Good About ADW's Flow Manager? Check out the 16.5 Release and See!
By Gerald "Jerry" Grzenia, Cadence

The 16.5 Allegro Design Workbench (ADW) Flow Manager has been enhanced to provide a more flexible and robust designer experience. It can now be launched in a stand-alone mode, is faster in launching, can open multiple flows, and you can customize it by adding new buttons!

Read blog »

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 Education Services

Latest additions to our Custom IC training portfolio

new Using Virtuoso Constraints Effectively vIC 6.1.5

This 2 day course is a practical examination of the way to set specific rules (=constraints) in the schematic that will be transferred to the layout design. There are a number of assistants, such as the Process Rules Editor, the Navigator, the Wire Assistant, and the Annotation Browser, all of which support passing the designers intent to the physical design. You can make changes in the layout that you can update back into the schematic.


new Cadence Library Characterization and Validation v3.1p3

During this 2 day course, you will learn the basic skills necessary to characterize and validate standard cell libraries using both Cadence Library Creation and Cadence Library Validation software tools. The course consists of both lecture and labs.

new Analog-on-Top Mixed-Signal Implementation vIC6.1.5

This newly developed training course targets experienced Analog Layouters and CAD Engineers who aim to implement designs in a Mixed Signal Environment. Within this 3 day training you gain experience in the area of Mixed Signal Implementation.

Upcoming Highlight - Save The Date

Analog Modeling and Simulation with SPICE

cdn LIVE EMEA 2011 The purpose of the course by Dr. Andrei Vladimirescu is to help circuit designers better understand semiconductor device modeling, with emphasis on Deep-Submicron (DSM) technology and the operation of a SPICE circuit simulator. The course also addresses the different levels of modeling, structural and behavioral, simulation controls available to the user and new types of analysis such as steady-state.

29th October - 1st November, Herzelia
6th-9th November, @ one of our European locations


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