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June 2010 Issue
 In this issue
In the news
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Manufacturability Sign-Off
Education Services
Custom IC Design
PCB & IC Packaging
Events & Webinars
 Quick links
Cadence blogs
Events
EDA360The way forward for electronic design
Twitter
Welcome to the June issue of eEuronews!

In recent weeks, Cadence has received a lot of supportive feedback on our new EDA360 vision. You may have seen the video of some of our customers responding to the many challenges that our industry will face in the near future. If you did not have a chance to watch, you will find all the latest news articles, customer videos, and the full EDA360 vision paper for download on our EDA360 microsite.

More videos about our latest product announcements, events, and customer testimonials are available at www.youtube.com/cadencedesign.

From June through September, we will be offering a series of 2010 Technology Updates for Encounter Digital Implementation System and Cadence Logic Design Solution. For more information, please click here. We also will be showcasing our silicon integration capabilities in the upcoming Technology on Tour series and highlighting news in the verification arena in our ClubT events.

For short and crisp news about seminars, interesting articles and news from Cadence EMEA, you can follow us now on Twitter.com/Cadence_EMEA.

And if you want to have a glance on what is happening in your design area, scroll down and take a look.

As always, we are happy to receive any feedback that helps to make this newsletter as useful as possible for you.

Best regards,

Wolfgang Stronski
EMEA Marketing Director at Cadence

 Cadence in the news
Cadence and IBM Team to Develop Leading-Edge IP >>

Cadence Announces Comprehensive SOI Design Hub >>

Cadence Delivers Extensive Support for TSMC Analog/Mixed-Signal Reference Flow 1.0 for 28nm Process >>

Cadence Delivers TLM-Driven Design and Verification, 3D-IC Design and Integrated DFM Capabilities to TSMC Reference Flow 11.0 >>

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 System Design and Verification
Using unified modeling methods to reduce embedded hardware/software development

Today's Internet devices are powered by sophisticated electronic circuits driven by multiple layers of software. These circuits are so complex they are called Systems on Chip (SoC) because they contain all the sub-components of a powerful personal computer. SoC development costs continue to grow rapidly, driven by increasing demand for more functionality, device mobility, and improved usability.

Functional verification of hardware, software, and their interactions is the other large and growing critical path component of a systems project. Complexity is growing with increased function integration on the SoC and software applications, exponentially driving up functional verification costs.

Read More >>

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 Functional Verification
Cadence Kick-Starts UVM Adoption with Open-Source Reference Flow Contribution to UVM World

Cadence is now providing the industry's most comprehensive open-source reference flow for system-on-chip (SoC) verification using the Universal Verification Methodology (UVM) standard. The unique flow enables engineers to adopt advanced verification techniques with reduced risk and deployment effort while meeting critical time-to-market requirements.

In support of the Cadence EDA360 strategy for delivering SoC Realization capabilities, UVM Reference Flow 1.0 provides a proven SoC design and UVM-compliant testbench components as open source for users to learn and apply advanced verification techniques. Users will be able to download the environment and instrument the UVM verification components to the design. This provides practical hands-on experience for applying the technology in an executable form when run on a UVM-compliant simulator. All code is provided in clear-text form so users can make modifications, apply different verification scenarios and precisely see the results of those changes.

Read More >>

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 Logic Design
Zarlink Speeds Design Closure by 2x with Cadence Logic Synthesis Technology
Encounter RTL Compiler with Physical Helps Zarlink Quickly Realize an Ultra-Low-Power RF Chip for the Medical Industry

As chips become smaller and more complex, and as concerns over power consumption take center stage, knowledge of physical feasibility is crucial input for design optimization. The uncertainty of physical interconnect timing can cause iterations between logical and physical design that do not converge. As a result, engineers are forced to choose: either meet their schedule or achieve their performance, power, and area requirements.

So that companies can optimize end-product quality and still hit their market windows, Cadence developed Encounter RTL Compiler with Physical. This product embeds Encounter® Digital Implementation System placement technology inside Encounter RTL Compiler's logic synthesis. Now, logical and physical design teams can see the same representation of a design, speeding closure on their overall design goals. The end result is a more predictable path to silicon realization that meets the most stringent product requirements.

Read More >>

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 Digital Implementation
3D IC Standards - First, Let's Define Our Terms
Blog by Richard Goering

There's a lot of interest in 3D ICs these days, but there are many challenges to solve before 3D IC design can move into the mainstream. One challenge is the establishment of standards for design, modeling, and manufacturability. But the starting point is likely to be something even simpler - a dictionary that defines a common taxonomy for 3D ICs.
Read more >>

Q and A: How Silicon Realization Changes IC Design
Blog by Richard Goering

As described in the EDA360 vision paper, Silicon Realization represents the creation of IP blocks, ICs, or systems-on-chip (SoCs) ready for software integration. But how is it different from EDA as we know it today, what are the challenges, and what solutions are needed? Sandeep Mehndiratta, Group Director of solutions marketing at Cadence, answers these and other questions in the following interview.
Read more >>

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 Manufacturability Sign-Off
What you didn't know about DFM for advanced node designs: "In-route" is insufficient
Blog by Manoj Chacko

Recently, there has been a lot of buzz about addressing DFM issues during routing. This is not a surprise as the economics of increased development cost of advanced process nodes and manufacturing has influenced dramatic changes to business models of several semiconductor companies.

Read more >>

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 Education Services
Training highlights

SystemVerilog Assertions completely revised to utilize the most effective use models >>
SystemC Synthesis using C-to-Silicon Compiler >>
Understanding High Frequency PCB Design - High-Speed, RF, and EMI >>
Cadence QRC User Transistor-level Extraction >>

New in Custom IC - v IC 6.1.4

Virtuoso Layout Design Basics
Virtuoso Connectivity-Driven Layout

Virtual classroom training - Contact us at eur_training@cadence.com for further details.

Download our latest training schedule. To receive a paper copy, please contact your local training representative.

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 Custom IC Design
Success Story: Mathworks Leverages Virtuoso AMS Designer

Using analog components in Virtuoso AMS Designer, Mathworks was able to verify system performance during the design phase, well before committing to silicon.

Read more>>

Cadence Knowledge Transfer Webinar Series

End of March Cadence held a webinar series to demonstrate the latest and greatest features in Virtuoso IC 6.1.4. The webinar recordings are now available on the Cadence Online Support Web where you can view the videos at any time.

New Layout Productivity Features in Cadence® Virtuoso® IC 6.1.4

Traditionally custom layout has been a manual and time consuming process. See how new functionality within Virtuoso® IC 6.1.4 can increase productivity by reducing the number of mouse clicks, make intelligent choices, and aid a layout designer to complete everyday tasks in a smarter and easier fashion.

Click here>>

Mixed-Signal Simulation for Analog Designers

This webinar will cover various methods of including digital RTL/Netlist into your mixed-signal design and verify it using AMS Designer.

Click here >>

You need a Cadence Log In to access this content. If you haven't created one yet, you can do it here.

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 PCB & IC Packaging
Blog: Favorite Features Of An IC Package Designer: Rich And Diverse Set Of Import And Export File Formats
This is the second in a series of discussions we would like to open up regarding "favorite features" in an IC Packaging implementation design tool.

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 Events & Webinars
2010 Technology Updates for Encounter Digital Implementation System and Cadence Logic Design Solution
During this highly technical series, you will hear presentations that include in-depth scenarios of digital design challenges that you may be struggling with today, as well as the latest features and functionalities of the Encounter Digital Implementation System and the Cadence Logic Design Solution that will help you overcome such challenges.

Event details >>

Finish Your High-Performance Digital Design on Time! - June 29, 10am PDT
Attend this webinar and find out how to finish your high-performance digital design on time. Prototype your designs effectively and use the most optimized abstraction models to implement your design with the best quality of results (QoR). Learn how a multi-CPU infrastructure allows you to achieve your turnaround time goals, what the different multi-CPU schemes are, and the advantages and disadvantages of each. Most importantly, find out how to finish your design on time by integrating the signoff engine within implementation and signoff your designs with confidence.

Event details >>

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