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June 2012 Issue
 In this issue
In the News
Functional Verification
Custom IC Design
Manufacturability Signoff
Low Power
Digital Implementation
IP News
PCB and SiP design, IC packaging
System Design and Verification
Cadence Academic Network
Education Services
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Welcome to the June edition of eEuronews!

For all of our readers who could not make it to join hundreds of Cadence technology users at the last
cdn LIVE EMEA 2011
CDNLive! Best Paper Celebration Video
CDNLive! EMEA user conference, we uploaded a number of videos that captured the highlights of the event. Please visit our CDNLive! Multimedia Channel 2012 to find videos of the keynote speakers, including the presentation of Luc Van den hove,
CEO at imec. You will see videos of the latest expansion to the Cadence System Development Suite and expanded support for accelerated VIP, the Best Paper celebration, the successful Academic track and many others.

On cadence.com you'll find the list of the Best Paper winners and a login to download the CDNLive! conference proceedings. If you don't have a Cadence log-in, you'll need to create one in order to access the presentations.

To get a short insight of what took place during the conference and why you shouldn't miss the next CDNLive! in May 2013 click the following video: cdn LIVE EMEA 2011
You will receive the next issue of the eEuronews early September after our editorial summer break.

Enjoy your summer!

Best regards,

Alexander Duesener
Vice President, Worldwide Field Operations - EMEA
Cadence Design Systems

 News
Cadence Announces STMicroelectronics has Taped Out 20-Nanometer Test Chip Using Cadence Tools »

Cadence Expands System and SoC Verification Offerings to Accelerate System Integration and Reduce Time to Market »

Cadence Collaborates on 3D-IC Design Infrastructure with TSMC »

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 Functional Verification
7 Years After Verisity - How Specman and e Language Changed IC Verification
Blog by Richard Goering, Cadence

Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random testbench generation, metric-driven verification, and significant use of verification IP (VIP).

Read blog »

Cadence says it's strong in Specman "e" yet language neutral
Deep Chip

Latest post on spread of "e" language by Kishore Karnane

Read post »

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 Custom IC Design
Things You Didn't Know About Virtuoso: Rapid Adoption Kits
Blog by Stacy Whiteman, Cadence

This post isn't directly about tips and tricks for getting the most out of Virtuoso, but it is about a new source of information and hands-on guidance to help you put those tips and tricks into action.

They're called Rapid Adoption Kits, or-to use the obligatory Three Letter Acronym (TLA)-RAKs.

Read Blog »

3D ICs and analog chips. Where's the match? Is there a match?
EDA 360 Insider - By Steve Leibson

Dr. Venu Menon, VP of Analog Technology Development at TI, gave a deeply informative lunchtime keynote speech at this week's ISQED Symposium. Most of Menon's presentation discussed analog process technology: what's important to analog chip design and manufacturing, what's changed over the years, what are the differences between analog and digital IC processes, etc. However, one slide in particular caught my eye as a perfect topic for this week's 3D Thursday.

Read Blog »

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 Manufacturability Signoff
Modeling stress-induced variability at advanced IC process nodes
EE Times Europe - By Philippe Hurat and Fang-Cheng Chang, Cadence

As design teams move to IC process nodes at 40nm and below, timing and power variability become more and more of a concern. To maximize system performance and meet timing and power goals, designers must find ways to model and mitigate variability.

Read article »

Cadence Pattern-Matching Technologies Accelerate Full-Chip DFM Signoff at GLOBALFOUNDRIES

GLOBALFOUNDRIES provides technologies for advanced silicon manufacturing at 130nm down to 20nm. To guarantee high yield and manufacturability at advanced process nodes like 32/28nm, GLOBALFOUNDRIES needed to go beyond traditional design-rule checking (DRC) and develop a new set of incremental design-for-manufacturing (DFM) verification methodologies. cdn LIVE EMEA 2011
View video »

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 Low Power
Hierarchical methods for power intent specification
EE Times - By Luke Lang, Cadence Design Systems

The intent of this design article is to provide a comprehensive tutorial on both the value of and the "how to" in using a hierarchical low-power design methodology.

Read article »

Power 108: Powering forward
EE Times

Survey about predictions where low power design would be in three years and ten years from now.

Read survey »

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 Digital Implementation
Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions
Blog by Richard Goering

At a recently archived EE Times webinar May 1, representatives of Cadence, ARM and TSMC noted three important points about the 20nm process node.

Read blog »

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 IP News
Cadence Announces Updated Design and Verification IP for DDR PHY Interface
Cadence announced that the company's comprehensive suite of DDR controller and DDR PHY design IP as well as its Cadence Verification IP Catalog now support the latest release of the DFI specification, version 3.1 (also announced today by the DFI Group).

Read press release »

Nufront's Third-Generation Mobile Applications Processor Powered by Cadence DDR3/3L/LPDDR2 Memory Interface IP Solution
Cadence announced that Nufront's NS115 chipset integrated the Cadence configurable DDR3/3L/LPDDR2 Memory Controller and Hard PHY IP core in its dual-core ARM® Cortex™-A9 based mobile applications processor.

Read press release »

Cadence Introduces New NVM Express IP Solutions for Solid State Storage Applications
Cadence launched the industry's first IP subsystem for the development of SoCs supporting the NVM Express 1.0c standard, an interface technology used in the rapidly growing solid-state drive (SSD) market.

Read press release »

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 PCB and SiP design, IC packaging
Cadence OrCAD Capture Marketplace Now Available on Desktop Browsers

Cadence announced the availability of its ground-breaking Cadence® OrCAD® Capture Marketplace to the entire OrCAD and Allegro® PCB design community through a standard desktop browser, as well as the addition of several new apps and a trial period for paid apps.

Read press release »

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 System Design and Verification
cdn LIVE EMEA 2011 Cadence Announces New In-Circuit Acceleration Capability and Expanded Support for Accelerated VIP

To help customers streamline their verification process for complex systems and SoCs, and to speed the delivery of next-generation consumer and wireless electronics products, Cadence has expanded our System Development Suite and Verification IP (VIP) Catalog with new capabilities for acceleration and emulation.

The System Development Suite now supports in-circuit acceleration, based on the Verification Computing Platform (Palladium XP) and the Incisive Verification Platform. In-circuit acceleration delivers-in a single environment-speed, connectivity to real-world interfaces of our industry-leading in-circuit emulation technology, and the advanced debug capabilities of simulation acceleration.

View Videos, Demos, Collateral, Articles etc. about System Development Suite here »

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 Cadence Academic Network
Academic Track at CDNLive! 2012 EMEA

Continuing its success, the Academic Track at CDNLive! EMEA 2012 attracted more than 70 academic attendees, and a substantial number of industry professionals. Sixteen technical and non-technical presentations formed the 2-day academic track.

For the first time, a Special Session was introduced, which was dedicated to interesting innovations in education and industry/academia collaborations such as new approaches in undergraduate education in Lebanon or the Texas Instruments Africa Analog University Program established in Kumasi, Ghana; a program which aims for the proliferation of circuit design knowledge in Africa.

Click on image to see what Dr. Eckhard Hennig, Scientific Strategy Manager at the IMMS Institut für Mikroelektronik- und Mechatronik-Systeme, has to say about the advantages of being a member of the Cadence Academic Network and attending CDNLive! EMEA.

View video »
cdn LIVE EMEA 2011
Dr. Eckhard Hennig, Scientific Strategy Manager at the IMMS Institut für Mikroelektronik- und Mechatronik-Systeme

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 Education Services
new Using Virtuoso Constraints Effectively vIC 6.1.5

This 2 day course is a practical examination of the way to set specific rules (i.e. constraints) in the schematic that will be transferred to the layout design. After completing this course, you will be able to:

• Recognize how constraints are set and overwritten
• Use the Circuit Prospector to locate predefined structures and apply constraints
• Use the Process Rules Editor to create rules for exceptions and special cases
• Use the Wire Assistant to interactively create interconnect
• Use the SKILL language to automate repetitive constraint applications
• Set environment variables to enable the use of constraints
• Set constraints in the schematic
• Set up process rule overrides
• Use the Annotation Browser to assist identification
• Set up constraints for MODGENS
• Set constraints for interactive and automatic place and route
• Set up the Dynamic Abstract Generator
• Write SKILL code to create constraints
• Use the Physical Verification System to verify constraints
• Understand the environment variables necessary for constraints

new Cadence Library Characterization and Validation v3.1p3

During this 2 day course, you will learn the basic skills necessary to characterize and validate standard cell libraries using both Cadence Library Creation and Cadence Library Validation software tools. The course consists of both lecture and labs.

new Virtuoso Visualization and Analysis XL vIC 6.1.5

In this course, you use the Virtuoso® Analog Design Environment L software to set up and control analog and mixed-signal simulations. You run analog simulations with the Spectre® simulator. You view the results in the new Virtuoso Visualization and Analysis (ViVA) XL tool waveform viewer which is modified from IC 6.1.5 and is now the default post-simulation analysis tool for the L/XL/GXL licenses of the Analog Design Environment. You learn to work with its available assistants and workspaces. You also learn to manage results databases and write analytical expressions using the Calculator tool.

Cadence Training Brochure 2012

Training at a glance - discover our flexible training delivery methods - Live, Virtual and Online (iLS) trainings, and browse through the comprehensive Learning Map of your interest. Download the PDF version here, or contact us for a complimentary printed copy.

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