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July/August 2011 Issue |
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Welcome to the Summer edition of eEuronews!
With entering into the summer and vacation period, I would like to bring to your attention that we have lots of archived webinars, which may show new ways of approaching your design challenges or to ease day-to-day tasks. Also the CDNLive! EMEA proceedings are now available for everyone with a Cadence log-in. If you do not have one, it takes only a few steps to create your own.
Just a few days ago, Cadence announced the acquisition of Azuro. Azuro offers unique clock concurrent optimization technology, also known as ccopt, which delivers superior capabilities for designers faced with increasing performance, power and area challenges. We will offer the Azuro ccopt technology immediately as an upgrade add-on for Cadence EDI customers.
We are also very proud, that in regards to virtual prototype solution, three of the four hardware/software development platforms of the Cadence System Development Suite have now become part of the TSMC Reference Flow 12.
In every quarter we draw a winner from customers that have completed the feedback survey form after attending one of our events. This time the winner is Valeria Garofalo, from Marvell in Italy. Congratulations! Valeria has won an iPod nano.
Best regards and enjoy the summer,
Wolfgang Stronski
Marketing Director EMEA, Cadence |
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| System Design and Verification |
Low power: The key issue for system integration in mobile devices
Embedded Computing Design.com
By Pete Hardee, Cadence Design Systems
The hardware and software worlds are colliding, and integration is providing a spark that will require system developers to keep a sharp eye on overall power demands. Innovative techniques can enable developers to validate whether software is correctly controlling the power-saving capabilities in the hardware platform and verify that the device can meet the power requirements in real system conditions.
As the lines blur between hardware and software development and integration, engineers tend to overlook the importance of developing these systems with power in mind. Even if a hardware design is optimized, the embedded software delivered within these systems must correctly and efficiently use the power-saving capabilities built into the hardware.
Teams developing these latest and greatest electronic systems need techniques focused on relieving the pressure of hardware/software integration. Techniques such as Power Shut-Off (PSO, also known as power gating), Multi-Supply Voltages (MSV), and Dynamic Voltage and Frequency Scaling (DVFS) can leverage platforms and advanced system-level verification capabilities such as emulation. Engineers require new forms to measure and dynamically analyze power requirements for integrating embedded software with hardware, which must be tested in real-world system modes by leveraging virtual platforms.
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| Logic Design |
Cadence blog: User View: A "Structured" Approach to Managing ECOs
Engineering change orders (ECOs) are inevitable, but the need to restart chip layouts is not. Engineers at Cisco Systems' ASIC design center in Ottawa, Canada, are having good success with complex functional ECOs using a combination of manual scripts and the Cadence Encounter Conformal ECO Designer, according to Sid Allman, hardware engineering manager at Cisco.
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| Functional Verification |
Cadence blog: Celebrating the Success of the UVM World Web Site
Cadence announced at the end of June that it had donated the UVM World Web site (www.uvmworld.org) to Accellera. This is a significant event for at least three reasons. First, in light of Accellera's recent release of the Universal Verification Methodology (UVM) standard, it is the right time for the organization the take control of the primary Web source for UVM information. It saves Accellera a good deal of time and money to build on this well-established and widely-used site rather than starting from scratch. The expectations is that UVM World will become even better and even more useful going forward.
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| Custom IC Design |
Press release: austriamicrosystems releases new versions of its best-in-class process design kit for 0.18µm High-Voltage CMOS technology
Based on Cadence® Virtuoso® custom design platform (both, IC 5.1.41 and 6.1.4 releases), the new HIT-Kits significantly improve the time-to-market for highly competitive products in the analog intensive mixed signal, smart sensor and System-on-Chip arena. Supporting designers in creating their first-time-right mixed signal designs even for complex designs, this comprehensive design environment with its highly accurate simulation models and flexible SKILL-based PCells provides a proven route to silicon.
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User View: Bringing Digital Control Logic into Analog ICs
Video interview with Thomas Moerth, austriamicrosystems
austriamicrosystems is an analog IDM that designs and manufactures ICs for applications such as power management, sensors, and sensor interfaces. But the company is not purely "analog." Most of its analog ICs have small amounts of digital control or bus interface logic, said Thomas Moerth, manager of design support at austriamicrosystems. Even though this digital logic may be only 10K-50K gates, it creates challenges such as finding the right speed/accuracy tradeoffs for top-level simulation.
View video »
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| Digital Implementation |
CDNLive! EMEA: Implementation strategies for a High Performance Cortex-A15
By Andrew Lambert, ARM, and Jerome Pierre-Justin, Cadence
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CDNLive! EMEA: Low-Power design challenges - an implementation perspective
By Stephen O'Loughlin, imec
Download PDF »
Please note that the CDNLive! EMEA proceedings are accessible only via your personal Cadence log-in.
Cadence blog: Q&A: Jim McCanny Discusses Altos Design and Fast IP Characterization
In May 2011 Cadence announced the acquisition of Altos Design Automation, a provider of ultra-fast characterization tools that model timing, noise, power, and process variations for "foundation" IP (standard cells, I/Os, memories). In this interview Jim McCanny, co-founder and former CEO of Altos, discusses the company's mission and technology, the increasing need for fast and accurate characterization, how fast characterization boosts IP reuse, and how Altos and its customers will benefit from the Cadence acquisition.
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| PCB and SiP design, IC packaging |
What's Good About Allegro PCB Router Region Rules? 16.5 has a few new enhancements!
By Gerald "Jerry" Grzenia
Designers normally create nets or groups of nets to assign constraints. This leads to nets rules, net class rules, and net class to class rules. As the size of physical symbols (footprints) is reducing, the need for region specific rules is also increasing.
When all these constraints are applied, the amount of memory consumption by the Allegro PCB Router increases. In 16.5, proper use of Net class and Net-class to class rules and region rules can significantly reduce the memory consumption.
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| Education Services |
 In our training portfolio: Analog-on-Top Mixed Signal Implementation
This newly developed training course targets experienced Analog Layouters and CAD Engineers who aim to implement designs in a Mixed Signal Environment.
Within this 3 day training you gain experience in the area of Mixed Signal Implementation. Day 1 is an introduction to Cadence Encounter Digital Implementation (EDI) and enables you to run the first basic steps in Encounter. The following days you learn how to handle a digital block inside Virtuoso and run Digital Implementation in Encounter, as well as understand how to analyze the Timing on Top-Level and finalize the implementation.
Please contact your local training contact for further details. |
Virtual Classes and Dates Available
Virtual Classroom is a web-based environment that allows you to participate in live training events without the need to travel. You listen to lectures, participate in lab exercises, ask questions, and receive feedback just as you would do in a conventional classroom. It saves the hassle, expense, and travel time to a training site.
Have a look at our complete offering --> select view: "Virtual Class" 
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In Allegro v16.5