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September 2011 Issue
 In this issue
In the News
Cadence Events
Logic Design
Functional Verification
Custom IC Design
Manufacturability Signoff
Digital Implementation
PCB and SiP design, IC packaging
Education Services
 Quick links
Cadence blogs
Events
Twitter
Welcome to the September issue of eEuronews!

For most of us in Europe, the month of September marks the end of the summer break, and sets the stage for a fast approaching fourth quarter.

We used the last weeks to prepare a series of webinars, seminars and events to take place in the upcoming months. Our main concern is to give our customers the most efficient, easy and cost saving way to receive the latest updates on the newest features of our design solutions.

We start the list of events with the annual CDNLive! user conference in Tel Aviv, Israel on Sept 26. We are looking forward to meeting our Israeli and international users. It will be a great opportunity for discussion and exchange personal design expertise with other peers and experts from Cadence.

CDN Live | Israel 2011
In this newsletter we have listed all the events focused on the EMEA region. If you want to get a full view on all Cadence events please visit our homepage here.

Now, I would like to address the SoC engineers amongst our customers. If you are assembling complex SoCs, you know that more than ever it is about integrating and optimizing standard IP blocks targeting specific end user applications. At Cadence our focus is on delivering highly differentiated IP for memory, storage, and high performance interfaces. Get a glance at our offerings and download the latest datasheets here.

Enjoy the newsletter!

Best regards,

Alexander Duesener
Vice President, Worldwide Field Operations (EMEA), Cadence

 News
Cadence and Imec Collaborate to Offer Shuttle Program to Indian Universities »

Altis Collaborates with Cadence Services to Deliver State-of-Art Design Kits »

Cadence and GLOBALFOUNDRIES Significantly Speed Design for Manufacturing Signoff at 32, 28 Nanometers »

Angstrem-T introduces a new PDK and FDK custom and semi-custom development platform based on Cadence mixed-signal solution »

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 Cadence Events
CDNLive! Israel
Sept. 26, 2011, Tel Aviv
Avenue Convention and Events Center, Airport City

CDN Live | Israel 2011
EDA360 - System Realization Webinar

Debugging Linux-based systems on Multi-core SoCs
21 Sep 2011 - Online, 3pm (GMT) 4pm (CET)


System Realization Fall Seminar Series

Please join us for an in-depth seminar focusing on the latest methodologies and technologies for system design and verification from Cadence.

04 Oct 2011 - Grenoble, France (Novotel Grenoble Centre)
06 Oct 2011 - Munich, Germany (Cadence Office)
11 Oct 2011 - Eindhoven, The Netherlands (High Tech Campus)
13 Oct 2011 - Bracknell, UK (Cadence Office)

ViVA IC615 Webinar - See the New Graphing Technology
22 Sep 2011 Online 1:00pm (CET), 12:00 noon (GMT)
Register »

SAME Visit us at SAME, Sophia Antipolis, France, Oct 12-13, Booth No. 9

Attend tutorials and technical sessions presented by Cadence engineers.



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 Logic Design
Cadence blog: How Imec and Cadence "Wrapped Up" 3D-IC Test

One of the most challenging aspects of 3D-IC development involves the testing of vertical die stacks with through-silicon vias (TSVs). You have to propagate test data up and down through the stack, verify the functioning of TSVs that are too small to probe, and isolate the individual dies you want to test. A recent collaboration between Cadence and the Belgian research institute imec helped ease some of these problems by developing an automated 3D-IC DFT architecture. he collaboration was aimed at both pre-bond (or "wafer") testing, which occurs before the dies are stacked, and post-bond testing, which occurs after two or more dies are stacked. Although difficult, pre-bond testing is important because it's a lot less expensive to find defects before the dies are placed in a stack. Imec is well known for its 3D-IC research, and the collaboration leveraged and extended work already done at imec in 3D-IC test.

Read More »

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 Functional Verification
Get control of ARM system cache coherency with ACE verification
EETimes.com - by Mirit Fromovich, Pete Heller, and Yoav Lurie, Cadence

Cadence announced at the end of June that it had donated the UVM World Web site (www.uvmworld.org) to Accellera. This is a significant event for at least three reasons. First, in light of Accellera's recent release of the Universal Verification Methodology (UVM) standard, it is the right time for the organization the take control of the primary Web source for UVM information. It saves Accellera a good deal of time and money to build on this well-established and widely-used site rather than starting from scratch. The expectations is that UVM World will become even better and even more useful going forward.

Read More »

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 Custom IC Design
Realizing the Promise of Electrically-Aware Custom IC Design
Electronicdesign.com - by David White

The challenges facing designers of the next generation of devices such as multimedia smartphones, tablets, and other mobile devices are many. They have to deliver highly responsive systems yet must also consume the least power possible-certainly no more than their competitors.

To achieve these goals, designers have been employing multi-processor architectures for many years. However, the need for even greater performance has exceeded the capability of current multi-processor/multi-cluster architectures.

Squeezing every last drop of performance and power out of these compute clusters is more important now than ever. One of the largest areas of opportunity for performance gains in multi-processor systems is in moving software-based cache-coherency management into hardware.

Read more »

SKILL for the Skilled: Introduction to Classes - Part 1

In the previous couple of SKILL for the Skilled postings, we looked at some of the features of SKILL++. In fact, we saw local functions, higher-order functions, and lexical scoping. Still another set of features of SKILL++ is called the SKILL++ Object System. This system provides a standardized way of implementing object oriented SKILL applications.

Read more »

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 Manufacturability Signoff
Who else wants to see a 60x speedup in DFM signoff on a 28nm design?

Rambus has announced that it achieved a 60x speedup in DRC for an IP design targeting a 28nm process technology using GLOBALFOUNDRIES' DRC+ methodology. This approach to DRC is interesting because it's the industry's first approach to DRC that teams silicon-validated libraries of yield-critical patterns with automatic pattern classification and pattern matching.

Read more »

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 Digital Implementation
Cadence blog: Why Cadence Bought Azuro - A Closer Look

Cadence announced July 12 its acquisition of Azuro, a provider of "clock concurrent optimization technology" (ccopt). But why, given that Cadence already has clock tree synthesis inside the Encounter Digital Implementation Platform? The answer is that Azuro technology goes far beyond clock tree synthesis to provide a new IC physical implementation approach that offers compelling power, performance, and area advantages.

Read more »

White Paper Summary: How to Succeed at 20nm

The upcoming 20nm process node promises tremendous advantages in power, performance and area - but it's also very challenging in terms of design complexity, lithography, and manufacturability. A newly published whitepaper from Cadence, summarized here, sets forth an approach that can mitigate the challenges of 20nm.

Read more »

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 PCB and SiP design, IC packaging
What's Good About ADW's Server? 16.5 Has a Few New Enhancements!

SAME Some of the enhancements to the Allegro Design Workbench (ADW) 16.5 release were introduced in the 16.3.1 release. The 16.5 version has expanded on these with an emphasis on increased performance.

Read more »

What's Good About Power Pins in SCM? The Secret's in the 16.5 Release!

The 16.5 release of the Allegro System Connectivity Manager (SCM), also known as Allegro System Architect (ASA), has been enhanced to view implicit power pins in the Component Connectivity Pane (CCP).

This is required for control over the power pins for the design with dies or FPGAs where an ECO is required. This is also required in the co-design flow for SiP where connectivity changes are updated using the ECO Netlist.

Read more »

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 Education Services
New In our training portfolio: Analog-on-Top Mixed Signal Implementation

This newly developed training course targets experienced Analog Layouters and CAD Engineers who aim to implement designs in a Mixed Signal Environment.
Within this 3 day training you gain experience in the area of Mixed Signal Implementation. Please check here for a detailed agenda.

New in Virtuoso 6.1.5

Virtuoso Analog Design Environment v IC6.1.5
Virtuoso Connectivity-Driven Layout vIC 6.1.5
Virtuoso UltraSim Full-chip Simulator vMMSIM 10.1

New In Allegro v16.5

Allegro High-Speed Constraint Management v16.5
Allegro PCB Editor v16.5

New Virtual Classes and Dates Available

Virtual Classroom is a web-based environment that allows you to participate in live training events without the need to travel. You listen to lectures, participate in lab exercises, ask questions, and receive feedback just as you would do in a conventional classroom. It saves the hassle, expense, and travel time to a training site.

Have a look at our complete offering at cadence.com/training/eu --> select view: "Virtual Class" Select view: Virtual Class

Upcoming dates:

10th-14th October SystemC Language Fundamentals v9.2
7th-11th November Virtuoso Analog Design Environment vIC6.1.5
24th-28th October Perl for EDA Engineering v2.0
28th Nov - 2nd Dec Analog Modeling with Verilog-A v7.2
12th-13th December Logic Equivalence Checking with Encounter Conformal EC v10.1
14th-15th December Advanced Logic Equivalence Checking with Encounter Conformal EC v9.1

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