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October 2011 Issue
 In this issue
In the News
Cadence Events
System Design and Verification
Logic Design
Functional Verification
Custom IC Design
Manufacturability Signoff
Digital Implementation
PCB and SiP design, IC packaging
Education Services
 Quick links
Cadence blogs
Events
Twitter
Welcome to the October issue of eEuronews!

In this issue we cover all the details of our upcoming free one-day technical seminars. Over the next few weeks, you will have the opportunity to attend seminars featuring System Realization or Mixed-Signal Realization. In the last week of October, ClubT Verification seminars will be held in Feldkirchen, Germany and Grenoble, France. If those seminars cover some of your interest areas please register for one of the seminars. We would appreciate your support by forwarding that information to your colleagues.

In 2010, Cadence outlined a new vision for the electronic design automation industry called EDA360. In the White Paper included in this newsletter, we have listed the progress and Cadence's deliveries on the vision as of today. If you would like to see its development in one glance download the PDF here.

A final heads-up: in the next two weeks, you will receive the Call for Paper for CDNLive! EMEA 2012. We hope we can encourage many of you to submit a presentation abstract (paper) and to become part of an exciting and rich program which always is the central core of the conference.

Best regards,

Wolfgang Stronski
Marketing Director EMEA, Cadence

 News
X-FAB Qualifies Cadence Physical Verification System for All Process Nodes »

Cadence Enables ST-Ericsson to Achieve Significant Productivity Gain for its 40-Nanometer Baseband Chip Design »

Altis Semiconductor Standardizes on Cadence MaskCompose Reticle and Wafer Synthesis Suite »

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 Cadence Events
EDA360 Technology on Tour - ClubT Verification Seminars

Cadence invites you to its free, one-day ClubT seminars in Germany and France.

We will give you an update on verification solutions with Specman/e, Incisive Enterprise Simulator-XL, UVM e, VIP, CAST, Specman-AMS and our progress on the "Trailblazer" technology roadmap.

25 Oct 2011 - Munich (Cadence office), Germany
27 Oct 2011 - Grenoble (Novotel), France

EDA360 Technology on Tour - Silicon Realization Fall Seminars

Please join us for an in-depth seminar focusing on the latest methodologies and technologies for system design and verification from Cadence.

11 Oct 2011 - Eindhoven, The Netherlands (High Tech Campus)
13 Oct 2011 - Bracknell, UK (Cadence Office)

EDA360 Technology on Tour: Mixed-Signal Silicon Realization

Join us for this 1-day free seminar focusing on analog/mixed-signal design, implementation, and verification.

Explore the latest technologies and integrated flows from Cadence that will help you design higher performance chips and systems more efficiently. This year we will have a focus in all sections on best practices discussing and showing detailed demos of many front-to-back aspects of custom/analog design.

02 Nov 2011 - Edinburgh, UK
03 Nov 2011 - Bracknell, UK
08 Nov 2011 - Dresden, Germany
09 Nov 2011 - Leuven, Belgium
10 Nov 2011 - Eindhoven, The Netherlands
15 Nov 2011 - Milan,Italy
16 Nov 2011 - Grenoble, France

Search for Cadence webinars here »

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 System Design and Verification
Evolving Devices from "All in One" to "One for All"

Read Frank Schirrmeister's blog on his recent visit to the edaForum in Berlin. He gives a summary of the keynote speech by Prof. Dr. Hermann Eul, President of Intel Mobile Communications, IMC, the former Infineon division that is now part of Intel. Dr. Eul first noted how the mobile market exceeded previous volume predictions and how the predicted shift to the "All in One" device happened. He then outlined the challenges ahead - how those devices need to become "One for All" communications mechanisms as everything computes and connects.

Dr. Eul then expressed his seven wishes which were mostly directed at the EDA and embedded software (ESW) industries, setting requirements for system design tools from IMC's perspective.

Read more »

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 Logic Design
Design for Test (DFT) - New Challenges at Advanced Process Nodes

Design for test (DFT) doesn't get a lot of press these days, which is unfortunate, because the demands of DFT are dramatically increasing as designers move to smaller lithography nodes. New fault types, test compression, and faster automatic test pattern generation (ATPG) are becoming critical. Mike Vachon, group director of the Cadence Encounter Test product gives an overview of what Cadence presented at the recent International Test Conference (ITC) in Anaheim, Calif. Sept. 18-23, 2011.

"The complexity and the amount of effort that DFT and ATPG take is really growing quickly as designs move to smaller lithography nodes," Vachon said. He noted that companies are finding they need a lot more DFT expertise, and that DFT IP is becoming vastly more complex, leading to an increased reliance on EDA vendors to generate, validate, and insert that IP during the design process.

Read More »

Cadence Announces DFI 3.0-compliant Design and Verification IP

Enables Rapid Deployment of Next-Generation SoCs Supporting DDR4 Memory

Read More »

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 Functional Verification
Cadence Accelerates Adoption of Emerging Mobile Standards with Expanded Verification IP Portfolio

Cadence just announced new protocol and memory model verification IP (VIP) that will accelerate the adoption of the latest mobile standards. Through close collaboration with leading system and semiconductor companies, and standards bodies, Cadence is delivering VIP at a very early stage - in many cases, ahead of the final specification - helping mobile SoC and system manufacturers to be first to market with increasingly feature-rich mobile devices, such as smartphones and tablets.

"The need for increased computing power and sophisticated video, audio and storage on mobile devices has given rise to new standards that improve performance and power, while reducing development time and cost," said Ziv Binyamini, corporate vice president, research and development, System Realization Group at Cadence. "In order to leverage these standards, our customers need solutions that can accurately test the functionality of their design and ensure manufacturing success. Our extensive protocol expertise, combined with our track record of effectively verifying thousands of designs for over a decade, gives customers a proven path to success in the mobile market."

Read More »

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 Custom IC Design
Fuji Electric Cuts Development Time 25 Percent with Cadence Virtuoso Accelerated Parallel Simulator

"Our design team shifted from our traditional approach for a conceptual design to the Virtuoso Accelerated Parallel Simulator-based circuit simulation environment for the entire design process, and achieved the 25 percent reduction in the lead-time for custom/analog design," said Dr. Naoto Fujishima, general manager of Device Development Dept., Si Device Development Center, Electronic Device Laboratory of Fuji Electric.

Read press release »

Giantec Semiconductor Switches to Cadence Technology, Gains 30 Percent Productivity with Virtuoso Flow

Cadence Unified Virtuoso and Encounter Flows Deliver Power, Performance, and Productivity Advantage for Development of "Smart" Devices.

Read press release »

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 Manufacturability Signoff
Video: Easing the Design Challenges of Double Patterning at 20nm

Double patterning lithography will be essential at 20nm and below until at least 2014, according to Lars Liebman, distinguished engineer at IBM. But it need not be a huge burden for engineers. In a talk at the Cadence booth at the Design Automation Conference in June, and newly available in the video clip embedded below, Liebman described how double patterning works, what design challenges it poses, and how IBM and Cadence are working to minimize the challenges.

View video »

Fujitsu Standardizes on Cadence DFM Technologies for 28nm ASIC and Mixed-Signal Designs

Cadence Design for Manufacturing Gains Momentum as Fujitsu Selects "In-Design" Technology to Help Ensure Yield, Predictability and Faster Path to Silicon Realization.

Read press release »

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 Digital Implementation
3D-IC Design: The Challenges of 2.5D versus 3D
EETimes.com, Sept 14, 2011

In October 2010 Xilinx announced its use of a 2.5D through-silicon via (TSV) approach for their Virtex-7 FPGAs. This was followed by announcements from TSMC, Samsung, Nokia, Micron, and Elpida about using 3D-ICs with TSVs, showing that TSV technology has emerged as a proven and viable technology that offers compelling advantages in power, performance, form factor, and time to market. By making it possible to stack analog, digital, logic, and memory dies at different process nodes, 3D-ICs offer what may be the best alternative to the skyrocketing costs of advanced process nodes.

Read more »

White Paper Summary: How to Succeed at 20nm

The upcoming 20nm process node promises tremendous advantages in power, performance and area - but it's also very challenging in terms of design complexity, lithography, and manufacturability. A newly published whitepaper from Cadence, summarized here, sets forth an approach that can mitigate the challenges of 20nm.

Read more »

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 PCB and SiP design, IC packaging
What's Good About Allegro PCB Router HDI Via Tangency? Check Out 16.5!

High Density Interconnect (HDI) techniques are increasing in the PCB domain. HDI provides the ability to place components on both sides of the board and helps reduce the PCB layer stack. Allegro PCB Router started evolving in this direction from the SPB16.2 version with drill holes and microvias. In the SPB16.3 release, constraints for blind and buried vias, and stacked via enhancements, were provided.

With the SPB16.5 release, SPECCTRA provides ability to use inset/tangency and stagger via patterns.

Read more »

IPC-2581 Panel: A Spirited Discussion on PCB Data Transfer Formats

A lively panel discussion Sept. 29 revealed that PCB designers have some strong opinions about the data formats that convey design intent to manufacturing. Several audience members expressed support for the Gerber data format that has been around for over 30 years. But other audience members and panelists agreed that a more intelligent and up-to-date format is needed, and that an open industry standard called IPC-2581 appears to be the best way forward.

Read more »

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 Education Services
New SPICE Seminar - Learn from the author of "The SPICE book"

Dr. Andrei Vladimirescu will be hosting The SPICE Seminar at our Cadence Munich Training Centre, 29th November - 2nd December 2011 - last seats are available!

The purpose of the course is to help circuit designers better understand semiconductor device modeling, with emphasis on Deep-Submicron (DSM) technology and the operation of a SPICE circuit simulator. The course also addresses the different levels of modeling, structural and behavioral, simulation controls available to the user and new types of analysis such as steady-state, particularly suited for RF design. Participants will have an opportunity to experiment with the various concepts presented in the course on workstations.

THE SPICE BOOK cover
Learn more »

New Virtual Classes and Dates Available

Virtual Classroom is a web-based environment that allows you to participate in live training events without the need to travel. You listen to lectures, participate in lab exercises, ask questions, and receive feedback just as you would do in a conventional classroom. It saves the hassle, expense, and travel time to a training site.

Have a look at our complete offering at cadence.com/training/eu --> select view: "Virtual Class" Select view: Virtual Class

Upcoming dates:

7th-11th November Virtuoso Analog Design Environment vIC6.1.5
24th-28th October Perl for EDA Engineering v2.0
28th Nov - 2nd Dec Analog Modeling with Verilog-A v7.2
12th-13th December Logic Equivalence Checking with Encounter Conformal EC v10.1
14th-15th December Advanced Logic Equivalence Checking with Encounter Conformal EC v9.1

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