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September 2010 Issue
 In this issue

In the News
System Design and Verification
Functional Verification
Custom IC
Manufacturability Sign-Off
Digital Implementation
Education Services
Events
PCB Design

 Quick links

Cadence blogs
Events
Twitter
EDA360

Welcome to the September issue of eEuronews!

Over the last months, we've talked a lot about the need to adopt a more application-driven integration strategy. "The Transformation of EDA" describes the cause of this shift and the steps required to support application-driven development. We have been discussing with many customers how this change will affect their traditional design approach. Here in EMEA we have many customers that are already embracing HW/SW design, recognizing that you can no longer separate them. I would be keen to hear from you if you also foresee this trend and how your company will respond to it.

With the beginning of September and the end of the summer break, we lined up a series of seminars and events for you. You can sign up for the Technology Updates for Encounter Digital Implementation System and Cadence Logic Design Solution starting September 6 in Kista, Sweden, or join us at one of our annual "ClubT" seminars starting in Munich on October 6.

If you want to learn more about TLM-driven design or the Universal Verification Methodology (UVM), you can now download ebooks on these topics from Amazon (see information below).

Last but not least, I am happy to announce that Luc Sponga from ST Microelectronics in France participated in our feedback survey and is the lucky winner of an iPod nano.

Best regards,
Wolfgang Stronski

Marketing Director EMEA
Cadence Design Systems
Stronski@cadence.com

P.S. CDNLive! ISRAEL 2010 has opened for registration; come and join hundreds of users in Tel Aviv, October 18, 2010

 Cadence in the news
Cadence Aligns Workforce to Deliver on EDA360 Vision »

Cadence QRC Extraction adopted by STMicroelectronics for 40nm Analog/Mixed-Signal Design »

Fujitsu Adopts Cadence Encounter Conformal ECO Designer »

Hitachi Achieves 10,000 Times Performance Boost Using Cadence Technology to Verify Complex Design »

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 System Design and Verification
Cadence and ARM Collaborate to Create an ARM-Optimized System Realization Solution - Joint Effort Will Streamline Development Time of ARM Processor-based Devices

Cadence and ARM will develop an optimized System Realization solution for ARM processors that will enable an end-to-end flow including a full set of interoperable tools, ARM® processor and physical IP, services and methodology from embedded Linux to GDSII. To accelerate adoption of this solution, Cadence will provide a full complement of tutorials and education materials including two methodology reference books and extend their ecosystem of service, methodology and training providers.

Read More »

Sigma Design adopts Cadence Simulation Acceleration Techniques

For set-top box and consumer electronics OEM customers, quality and reliability are prime concerns, as the costs of dealing with product returns are usually prohibitive. Therefore, thorough and effective verification is a must.
What makes verification particularly challenging is having many complex IP components working together, orchestrated by several hundred thousand lines of embedded software. It's impossible to get the level of confidence needed by just exhaustively verifying portions of the system.

Read More »

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 Functional Verification
Comprehensive UVM/OVM Acceleration

Today's traditional design flow involves design at multiple levels of abstraction.

This white paper describes a consistent and comprehensive Universal Verification Methodology (UVM)/ Open Verification Methodology (OVM) that prescribes substantial reuse across multiple levels of abstraction and facilitates a metric-driven verification (MDV) flow. While this document focuses on UVM/OVM acceleration, it also touches on other abstraction levels, such as transaction-level modeling (TLM).

Read More »

Moving To Constrained-Random Verification

Sarmad Dahir, ASIC designer at Ericsson in Stockholm, Sweden, is part of a significant ongoing shift in functional verification - the move from directed testing to constrained-random test generation and metric-driven verification (MDV).

Ericsson has a long history of using constrained-random generation, especially at the block level. Dahir's team adopted this methodology for top-level verification of mobile platform ASICs. When Dahir joined Ericsson two and a half years ago, some of those ASICs were still verified using directed C language test cases. In such instances, he said, "there were two teams, one that developed the ASIC and another writing test cases in C. That was very time consuming. Sometimes the software was ready weeks after the hardware RTL was ready."

Read More »

New Cadence Publications:

TLM-Driven Design and Verification Methodology
Get your copy now. Industry experts discuss system-level design, including how high-level synthesis has reinvigorated the use of SystemC modeling and provided new opportunities to speed functional verification.

A Practical Guide to Adopting the Universal Verification Methodology (UVM)
UVM is based on a simple script conversion of the Open Verification Methodology (OVM) 2.1.1 and thereby inherits the quality and experience of ten years and thousands of successful verification projects

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 Custom IC
Cadence Virtuoso Update
By Daniel Payne, chipdesignmag.com

For this article David met with Cadence to get an update on the Virtuoso product line. If you want to get answers to questions such as:

Where does Virtuoso fit into EDA360?
How much more productive are Virtuoso 5.1 to 6.1 users?
What are some of the methodology issues that limit IC layout productivity?
The digital designers have a very automated process for simulation and verification. What do you offer the analog designer?
How is Virtuoso aware of manufacturing issues?
How do I get parasitic info into my analog simulations?


Read More »

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 Manufacturability Sign-Off
SMIC-Cadence Collaboration Delivers In-Design DFM Flow to Mutual Customers

Design-for-manufacturing (DFM) strategy has evolved from a "nice-to-have" into a "must-have". Systematic variations due to lithography, such as timing glitches, thickness variations, and hotspots, are the greatest cause of electrical malfunctions and catastrophic chip failures. Especially at complex 45nm processes, engineering teams need a comprehensive DFM flow to prevent, predict, detect, and correct the effect of variations on design performance and yield.

View the Video »

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 Digital Implementation
Programatically Capturing Cell Delay In The Encounter Digital Implementation System

A while back we were talking about how to programatically troubleshoot timing violations in Encounter. That post received a lot of good comments (thanks!) but one in particular touched on a point that I've worked on with other users, so I thought to raise it up for visibility here and go more in depth on the topic.

Read More »

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 Education Services
Virtual Classroom Trainings

- Live training without travel time and cost!
Secure your seat in the upcoming classes (half-day sessions):

Cadence QRC User Transistor-Level Extraction: 14th-17th September 2010
Encounter RTL Compiler: 14th-17th September 2010
SKILL Development of Parameterized Cells: 4th-7th October 2010

New training catalogue 2010 / 2011 - download it here

To receive a paper copy, please contact your local training department

Latest training releases:

SystemVerilog Advanced Verification Using UVM v1.0
  All attendees receive a complimentary UVM book!
SystemVerilog Design and Verification - v3.2
Encounter RTL Compiler v9.1
Virtuoso Layout Design Basics vIC6.1.4


All training courses and dates can be found at cadence.com/Training/eu or esperan.com

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 Events
Choosing the right Verification Language - Webinar:
15 September 2010, Online, 3:00pm GMT; 4:00pm CET

The following topics will be covered in the webinar:
• Common language misconceptions
• Verification characteristics that make languages important
• Important technical aspects to consider for each language
• Which language fits best, and where?



2010 Technology Updates for Encounter Digital Implementation System and Cadence Logic Design Solution

Dates and Locations:
• 6 Sep 2010 Cadence Office, Kista, Sweden
• 7 Sep 2010 Malmoe, Sweden
• 8 Sep 2010 Gothenburg, Sweden
• 10 Sep 2010 Trondheim, Norway
• 28 September 2010 Cadence Office, Milan, Italy



"ClubT"

Join us for one of our annual "ClubT" seminars, where we will give you an update on verification solutions with Specman/e, Incisive Enterprise Simulator-XL, OVM/UVM e and multi-language UVM, SystemC, ESL/TLM, VIP, CAST, Specman-AMS and our progress on the "Trailblazer" technology roadmap.

Dates and Locations:
• 06 Oct 2010 - Munich
• 08 Oct 2010 - Sophia-Antipolis
• 12 Oct 2010 - Grenoble
• 14 Oct 2010 - Bristol


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 PCB Design
Cadence Develops Die Model Enabling Comprehensive Chip-Package Co-Design Solution with Fujitsu
Solution Uses Encounter Power System and Allegro Package Designer to Implement Standard Format for Die Models, Enabling Accurate Package ASIC/MCU Analysis.


What's Good About DEHDL Anchor Point Wire Stretch? It's In SPB16.3!


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