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February 2011 Issue
 In this issue
In the News
System Design and Verification
Logic Design
Functional Verification
Custom IC Design
Manufacturability Sign-Off
Digital IC Design
Cadence Academic Network
Education Services
 Quick links
Cadence blogs
Welcome to the first issue of eEuronews and
Happy New Year 2011!

We started into the New Year with the introduction of a new digital end-to-end flow that addresses advanced giga-gate/gigahertz designs at 28nm. The new Encounter-based flow is driven by the Silicon Realization approach, which is a key element of the EDA360 vision. It is a unified digital design, implementation and verification solution that provides the fastest deterministic path to giga-gates/GHz, low power, mixed signal silicon realization. You will find all related information here.

We were very proud to conclude last year with receiving the Elektra Electronics Industry Awards 2010 in the category design tools for the Virtuoso APS (Accelerated Parallel Simulator). APS was competing against very strong nominees, but the jury decided that APS could make a real impact on design circles.

Our Allegro and OrCAD Software is now nominated as the Product of the Year by the German Elektronik editorial office. The awards ceremony will be held in Munich on March 17, 2011.

Last but not least, I would like to inform you that the CDNLive! EMEA paper submission is closed. As you may recall, we entered the early submitters into a prize draw. I am very happy to announce that Samuel Le Prunenec from Freescale won the iPod nano.

Best regards and a successful 2011 to all of you,

Wolfgang Stronski
EMEA Marketing Director at Cadence

Cadence Drives Giga-gate/Gigahertz Design at 28nm with New Digital End-to-end Flow »

Spreadtrum Standardizes on Cadence Design Flow and Achieves One-Pass Silicon Realization for Its First 40nm Product »

Cadence Introduces 32/28-Nanometer Low-Power RTL-to-GDSII Silicon Realization Reference Flow for Common Platform Alliance »

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 System Design and Verification
How an Emerging Methodology Better Supports SoC Design
By Steve Brown and Raj Mathur, Cadence

Fueled by massive functional capacity, high-performance and low-power silicon processes, and exploding software application content, the pace and scope of electronics innovation is accelerating. The challenges of forging increasingly complex systems are also growing, confronting traditional approaches with out-of-control verification costs and missed market windows. What's needed is a system design approach that allows both earlier software development and faster silicon development, along with earlier and more frequent system integration steps.

This methodology must enable a unified hardware/software development and verification environment, and allow the specification, analysis, and verification of constraints such as timing and power in the context of the software and the system. This article highlights recent advances in system design, transaction-level verification, and software development that support such a unified environment. The article discusses the role of standards and explains the productivity gains behind a transaction-level modeling (TLM)-to-GDSII design and verification flow.

Read More »

Cadence C-to-Silicon Compiler Supported in Fujitsu Semiconductor's ASIC Flow for System Realization

Fujitsu Semiconductor Limited now supports the Cadence® C-to-Silicon Compiler for high-level synthesis in ASIC design flows. C-to-Silicon Compiler is the only high-level synthesis tool that embeds production RTL synthesis--Cadence Encounter® RTL Compiler--to generate implementation-ready RTL for the target application. This delivers a predictable flow from transaction-level model (TLM) to GDSII, with the ability to apply ECO patches throughout, effectively reducing System Realization time. A separate Fujitsu subsidiary has already begun using C-to-Silicon Compiler in production on a large-scale design

Read More »

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 Logic Design
Cadence Silicon Realization Helps Teledyne Conquer Growing ECO Challenges

Teledyne Imaging Sensors (TIS) produces high-performance subsystems for space missions, long-range terrestrial surveillance, and astronomy applications. When a TIS engineering group tackled a new imager chip, it knew manual metal-only ECO changes would be too time- and cost-prohibitive to meet the project's stringent requirements.

Cadence Encounter Conformal ECO Designer helped TIS achieve a 3x gain in productivity and accelerate time to market. With Cadence, Teledyne was able to implement pre-mask functional ECOs, eliminate time-consuming iterations through automation, and decrease the risk of missing critical bugs with independent verification technology

Read More »

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 Functional Verification
Cadence Boosts Verification Productivity for Complex FPGA/ASIC Design

Cadence has announced new advancements to help boost verification productivity for ASIC and FPGA designers. Coupled with full support for the emerging Accellera Universal Verification Methodology (UVM) 1.0 industry standard, the 600-plus new capabilities expand the scope of metric-driven verification (MDV) to help engineers achieve faster, more comprehensive verification closure and Silicon Realization. With the new release of the Cadence Incisive® technology, verification engineers can merge coverage data from formal analysis and simulation engines within a unified verification plan. Additional abilities that expand the scope of the verification intent include support for enhanced low-power corruption and isolation simulation as well as automation for combining and mixing simulation and formal technologies.

Read More »

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 Custom IC Design
Cadence Virtuoso Accelerated Parallel Simulator wins Elektra Industry Award 2010

As a part of the Virtuoso Multi-mode Simulator provides the next generation SPICE accurate simulation, with scalable performance and capacity, for a broad class of complex analog, RF and mixed-signal blocks and sub-systems with ten thousands of devices. It is tightly integrated with the Virtuoso custom design platform and provides all the transistor-level analysis capabilities as in Virtuoso Spectre Simulator. The proprietary full matrix-solving algorithm delivers unparalleled scalable multi-threading capability using modern multi-core machines.

Download Datasheet »

Webinar: Remote Enablement for a Globalized Workforce - Cadence and Open Text Enable Optimized Performance

Attend this technical webinar to find out how Cadence and OpenText are providing a complete solution and competitive edge for companies in four key areas: Accelerate design schedules and reduce time to market; Do more work in less time; Maximize resources while reducing cost; Manage outsourced design projects.

Time and date: Feb 24, 2011, 4.00pm CET

For registration click here »

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 Manufacturability Signoff
STARC and Cadence Develop In-Design DFM for 32/28-Nanometer Silicon Realization

Cadence announced that it has teamed with the Semiconductor Technology Academic Research Center (STARC), a Japanese design consortium, and created an innovative new Cadence®-based 32/28-nanometer design-for-manufacturing (DFM) flow. Using the award-winning Encounter® Digital Implementation (EDI) System as the end-to-end implementation vehicle, the in-design DFM flow built into STARC's STARCAD-CEL methodology enabled chip DFM signoff up to 100 times faster than traditional industry DFM methods.

Read press release »

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 Digital IC Design
Cadence Charts the Fastest Path to 28nm Silicon Realization
Find press releases, collateral, events relating to the new announcement here
Whitepaper: Silicon Realization - a new approach to faster and more profitable silicon.
Blog: CDNLive! Silicon Valley 2010: User Papers Explore Digital Implementation

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 Cadence Academic Network
Cadence Academic Network gets Linked in

With the beginning of 2011, the Cadence Academic Network will provide its information via the LinkedIn network. It offers advanced possibilities to receive tailored information and a platform for discussion. The "Cadence Academic Network" group acts as the main portal, whereas the subgroups such as "Low Power Methodology" provide a platform for special interests in a particular technical field. The groups are moderated by the lead institutions of the academic network, ensuring a constant flow of information and discussions.

This initiative flanks the EUROPRACTICE / Cadence partnership, which is running successfully for over two decades. The EUROPRACTICE initiative provides access to Cadence tools for non commercial teaching and academic research. To have access you need to sign up first at LinkedIn.

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EDA360 Tech on Tour: Silicon Realization - ClubF

Date: 17 Feb 2011
Location: Cadence Design Systems, Mozartstr. 2, 85622 Feldkirchen, Germany

Don't miss the chance to extend your formal verification expertise and learn more about general advances in the field, the Incisive Formal and Enterprise Verification roadmaps in particular, and to network with other Formal and Assertion-Based Verification (ABV) power users. This is a deep dive, technical forum for intermediate and advanced users of Incisive Formal Verifier (IFV) and Incisive Enterprise Verifier (IEV).

Register here »

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 Education Services
New EMEA Training Schedule for H1 2011 released

Download it here or contact us to receive a printed copy.

Latest training releases:

SystemVerilog Advanced Verification Using UVM v1.0
  All attendees receive a complimentary UVM book!
Specman Elite Basics for Verification Environment Users v9.2
Floorplanning, Physical Synthesis, Place and Route (Flat) v10.1
Virtuoso Spectre Circuit Simulator vMMSIM 10.1
SC4-Transaction-Level Modeling (TLM 2.0) v10.2

iLS Training - Training Anytime, Anywhere

Internet Learning Series (iLS) are self-paced Cadence Education classes delivered over the web that let you proceed at your own pace, anytime and anywhere. These internet based courses include dynamic course content, downloadable labs, instructor notes and bulletin boards. Find a complete list at --> Category: Online CoursesOnline courses

Virtual Classes - Live Training Without The Need to Travel

Virtual Classroom is a web-based environment that allows you to participate in live training events without the need to travel. You listen to lectures, participate in lab exercises, ask questions, and receive feedback just as you would do in a conventional classroom. It saves the hassle, expense, and travel time to a training site.

Learn more >>

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