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December 2011/January 2012 Issue
 In this issue
In the News
Cadence Events
System Design and Verification
Logic Design
Functional Verification
Custom IC Design
Manufacturability Signoff
Digital Implementation
PCB and SiP design, IC packaging
Cadence Academic Network
Education Services
 Quick links
Cadence blogs
Events
Twitter
Welcome to the December/January edition of eEuronews!

First of all, I would like to take this opportunity to wish you all a successful year end and a prosperous 2012!

As part of our continued commitment to bringing our latest technology as close as possible to you, we visited 16 locations throughout the EMEA region during the month of October and November. We met with more than 400 users during our public seminars and another 200 at various customer sites. Our team is already in the process of preparing the 2012 schedule, so stay tuned for updates in the next newsletter.

For all of you that were not able to attend a seminar in person, we've saved the webinars to our archives so that you can access them and learn about all the new features that were presented.

Another important reminder, the deadline for submitting papers for CDNLive! EMEA 2012 is quickly approaching. Do make sure to send us your abstract no later than December 14th for consideration. This is an excellent opportunity to share experience with your peers, participate in industry networking and discover the latest design technologies. Now is the time to think about your valuable contribution.

At the end of the year, a lot of discussions focus on the trends and challenges facing the electronics industry. From my point of view, and related to the challenges Cadence faces as an EDA supplier, the realization of complex mixed-signal designs will keep us busy for quite some time. There is hardly any chip designed today that has not included both analog and digital blocks. Smartphones, tablets and any other mobile devices are the products that will continue to push the limits of today's existing technologies - this applies for our customers and it also applies to us.

I'd be very interested in hearing your point of view about what you believe will keep us busy in the near future. Send an email to stronski@cadence.com.

Best regards,

Wolfgang Stronski
Marketing Director EMEA, Cadence

P.S. The next edition of eEuronews will be in your inbox the week of February 1st, 2012!

 News
Cadence Wins TSMC EDA Partner Award for 3D-IC Technology »

TowerJazz Reference Design Flow 2.0 Fully Qualifies Cadence Mixed-Signal Solution and Process Design Kit »

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 Cadence Events
Advance Your Mixed-Signal Design and Verification Techniques

Virtually all modern IC and SoC designs are mixed signal. Most systems have to interface their millions of gates, DSPs, memories, and processors to the real world through one or more analog or mixed-signal subsystems, such as a display, an antenna, a sensor, a cable, or an RF interface.

Join Cadence R&D for two technical webinars on the most relevant topics in mixed-signal design and verification. We'll introduce you to the latest techniques, best practices and methodologies needed for designing and verifying your mixed-signal IP and SoCs. Please join us if you are an analog or mixed-signal design engineer, verification engineer or team manager. And you don't need to travel-you can view these webinars from the comfort of your home or office!

THE SPICE BOOK cover
Register online »

Webinar 1: Power Integrity Challenges in Mixed-Signal Designs, December 6 at 9am PST

Webinar 2: Advanced Technology to Verify Complex Mixed-Signal Designs, December 8 at 9am PST

Functional verification webinar: Set Your UVM Runtime Phases to Maximum Power - December 7 at 8.00am PST

The following topics will be presented:
• Identifying when UVM runtime phases are really required
• Basics of the UVM runtime phases - what the UVM BCL provides
• Applying the runtime phases using the UVM Reference Flow
• Common problems and solutions when applying runtime phases

Register online »

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 System Design and Verification
Cadence Palladium XP Enables QLogic to Rapidly Develop Sophisticated Network Switch

QLogic has deployed the Cadence Palladium XP Verification Computing Platform to speed the design of a complex network switch. QLogic manufactures Fibre Channel, 10Gb Ethernet converged networking and InfiniBand switches for storage and high-performance computing (HPC) applications. These switches provide the port-density and performance required to drive storage, data and HPC networks of leading OEMs and end users worldwide. Using the Palladium XP system, QLogic dramatically reduced the design time associated with developing a complex, multi-million-gate system-on-chip (SoC) needed to drive scalable, non-blocking switch architectures across the various protocols required from datacenter-class switching solutions.

Read more »

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 Logic Design
ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs
Blog by Richard Goering, Cadence

The 32nm and 28nm process nodes, the most advanced nodes currently in production, pose formidable challenges in complexity, power management, variability, and manufacturability. A recent ARM TechCon paper authored by Cadence and Samsung described a methodology that can resolve those challenges. And it's not just theoretical - the paper also showed how the methodology was applied to a groundbreaking HD digital camera system-on-chip (SoC) developed by semiconductor startup Ambarella.

First, a few words about the Ambarella A7L SoC, a chip that promises to usher in a new generation of HD video enabled digital cameras. Ambarella announced availability of the chip in September 2011, and Cadence and Samsung followed up Oct. 25 with an announcement of their collaboration on the chip. The A7L was designed using Samsung's 32nm low-power, high-k metal gate (HKMG) technology and ARM 32nm libraries along with the Cadence Encounter Digital Implementation System and Encounter RTL Compiler. The chip contains an ARM 1136, several million logic gates, and a number of high-speed mixed-signal blocks.

Read More »

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 Functional Verification
Archived Functional Verification Webinars

Cadence has been running a series of online webinars on various functional verification topics in 2011. Here is a selection of the archived webinars. You will find the complete list here >>

• Quickly Find Data Transport Bugs with Formal Scoreboarding
• What Metrics Matter - A User's Perspective on Coverage
• Oceans of Expertise Connecting the UVM to Sea (C /C++/SC)
• Automate Assertion Generation for Simulation, Formal and Emulation Flows
• Applying Digital Verification Methodologies to Analog Design
• Ending the Debate - Apples or PC's? e or SystemVerilog?
• Finding the Bugs in Your UVM Haystack

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 Custom IC Design
Simulation Spotlight: APS Parasitic Stitching Flow for improved Capacity and Productivity
by Robert Schweiger, Cadence

About two month ago Cadence has released Virtuoso Multi-Mode Simulation MMSIM 11.1 which is a comprehensive design and verification solution that combines SPICE, RF, FastSPICE, and mixed-signal simulators in a unique shared licensing package. Cadence continues to make significant improvements in MMSIM.

As designers are adopting advanced process technologies realizing more complex SoCs the number of parasitics is dramatically increasing. Parasitic re-simulation at the end of the design process is a challenging verification task that is at the critical path before tapeout.

In the past if a designer wanted to use Virtuoso APS for parasitic re-simulation then he had to decide between two flows:
   a) generate a flat netlist from the extracted view within Virtuoso
   b) generate directly a flat DSPF netlist out of the parasitic extraction tool
However the netlisting process in both flows is very time consuming since all parasitics are included.

In MMSIM11.1 we support now a parasitic stitching flow with APS for enhanced analog post layout verification. Analog designers are now able to use APS stitching to back-annotate parasitics and run simulation on the entire design with full SPICE accuracy.

THE SPICE BOOK cover
Parasitic stitching with APS has three major advantages compared to the two flows mentioned above:
   1. The stitching flow preserves the design hierarchy since parasitics are stitched into the pre-layout netlist
   2. Re-use your pre-layout simulation testbench which does not require changing the .probe or .measure statements.
   3. The APS stitching flow supports SPEF/DSPF and is consistent with the UltraSim stitching flow

Parasitic stitching also allows designers to do a what-if analysis through selective stitching.

The scope can be either a subcircuit or an instance. When a subcircuit is specified as the scope, parasitics are stitched to all the instances of that subcircuit. In addition designers can decide to stitch only R or C to a subcircuit or instance. All other parasitics are then ignored.

Log on for more details on MMSIM 11.1 »

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 Manufacturability Signoff
"In Design" DFM Signoff - the Inside Story
Blog by Richard Goering, Cadence

As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until right before tapeout to run all these checks at once. But how does it actually work and what are the advantages and tradeoffs? This blog post takes a closer look.

Read more »

GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?
Blog by Richard Goering, Cadence

DRC+, a pattern-matching design for manufacturability (DFM) technique developed by GLOBALFOUNDRIES in collaboration with Cadence, is heading for standardization through the Silicon Integration Initiative (Si2). As announced Oct. 20 at the Si2 Conference, GLOBALFOUNDRIES has donated DRC+ data structures to the Si2 DFM Coalition (DFMC), which will incorporate this technology into the emerging OpenDFM standard.

Read more »

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 Digital Implementation
Clock-Concurrent Optimization Reshapes IC Physical Design Flow
Chipdesignmag.com, Nov 2011- by Paul Cunningham and Steve Wilcox, Cadence

No modern, synchronous integrated circuit (IC) can function without a clock network. Clock-tree synthesis (CTS), which distributes clock signals to data registers, is a critical step in the IC physical design flow. But the traditional approach to CTS, which is based on minimizing clock skew and is separate from logic optimization, is breaking down for advanced-node, high-speed designs. The problem is that today's chip designers are facing a growing "timing gap" between the ideal clocks assumed pre-CTS and the more accurate propagated clocks, which emerge after CTS. This timing gap is driven by factors like clock gating for low power, on-chip variation, and design complexity. At 40/45 nm, the clock timing gap can be as much as 50% of the clock period. This makes it difficult for designers to close timing and impossible to fully optimize designs for timing, power, and area.

Read more »

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 PCB and SiP design, IC packaging
What's Good About ADW's Configuration Manager? The Secret's in the 16.5 Release!
By Gerald "Jerry" Grzenia on November 1, 2011

The Allegro Design Workbench (ADW) Configuration Manager application is designed for an administrator to manage the ADW environment including:

• Server / Client Installation Configuration
• Company and Site configuration
• Server status
• Metrics Dashboard

It provides a single location where the ECAD environment can be managed and reported on. In ADW 16.5 the focus has been on:

• Site Management
• Metrics Dashboard

Read on »

What's Good About Refresh, Copy Project, TCL in SCM? 16.5 Has a Few New Enhancements!
By Gerald "Jerry" Grzenia on November 1, 2011

There are several enhancements in the 16.5 System Connectivity Manager (SCM) / Allegro System Architect (ASA) product that I've compiled below that I'm sharing in a brief post this week. Please take advantage of these new 16.5 capabilities.

Read on »

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 Cadence Academic Network
With CDNLive! EMEA 2012 on its way, we would like to bring to your attention that a number of submitted papers for the academic and the industrial track will be selected by the Technical Program Committee for inclusion in a special issue of the Journal Of Low Power Electronics (JOLPE). The authors of these selected papers will be invited to submit an extended and revised version in order to pass the journal's review process.

This special issue is expected to be published in the first half of 2013.

Don't miss to get a broader exposure of your contribution by submitting an abstract for CDNLive! EMEA 2012. Submission deadline is Dec 14th, 2011.

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 Education Services
New 2012 Schedule Released

Have a look at cadence.com/training/eu and esperan.com to find our dates planned for January-June 2012. Our Education Services team is happy to assist in finding the right training for you, so feel free to contact us.

Internet Learning Series (iLS)

Did you know we offer over 50 courses in Internet Learning Series (iLS) formatting? Our internet based courses include dynamic course content, downloadable labs, instructor notes and bulletin boards. Available within 3 days, 24/7.

Have a look at our complete offering at cadence.com/training/eu --> select view: "Virtual Class"
Select view: Virtual Class

Special Promotion - Understanding High Frequency PCB Design - High-Speed, RF, and EMI -v3.0

This unique course will run at our Bracknell training centre, 12th-16th December 2011. Contact us for further information on our special promotional offer. The first part covers essential high-speed PCB design for signal integrity, the second part gives an overview of PCB design at RF - multi-Gigabit transmission, EMI control, and PCB materials. The course is suitable for Design engineers seeking in-depth knowledge of high-speed PCB design, signal integrity issues, high frequency effects and EMC, as well as PCB designers working on digital or mixed signal boards with design rules governing track impedance control, line terminations, routing to minimise noise coupling etc.

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