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January 2013 Issue
 In this issue
Cadence News
Cadence Events
Custom IC Design
Digital Implementation
Functional Verification
System Design and Verification
Low Power
Manufacturability Signoff
IP News
PCB
Cadence Academic Network
Education Services
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Welcome to the first edition of eEuronews 2013!

What to expect from 2013? Several renowned industry analysts such as Gartner project solid growth for the semiconductor industry in 2013 in the mid-to-high single digit range. Traditional PC related semiconductor revenue will decline dramatically, whereas non-PC growth is expected to be double digit, due to strong demand in smart phones, tablets and automotive. One clear trend to watch out for is that software is becoming a critical differentiator across these markets including automotive. Hence concurrent hardware-software engineering expertise has become a key factor in meeting time-to-market and quality requirements.

But how do you deliver increasingly complex hardware and software intensive products to market reliably, with high quality, and simultaneously drive down development costs? To answer these challenges, Cadence will exhibit at the "embedded world 2013" conference in Nuremberg from Feb 26-28 under the motto "Prototyping and Early Software Development". Join us and learn more about the Cadence System Development Suite which is composed of four open and connected platforms for concurrent hardware/software design and verification. There will be a variety of live demos from Virtual Prototyping, FPGA based prototyping and Emulation based hardware-software verification solutions. And for engineers working on Automotive-Ethernet based systems, we will showcase a live demo of the Cadence Automotive Design IP and Verification solution, announced in December.

For a free entrance pass and pre-registration use the following link:
www.embedded-world.de/e-voucher and enter code: 261520.

For more information about the latest developments in your respective design space, please view below.

Best regards,
Christian Malter
Director Technology Solutions, EMEA

P.S. The winner of the iPad3 price draw is Arthur Freitas from Freescale in Toulouse, France, for submitting his paper on time. Congratulations!


 Cadence News
ARM and Cadence Tape Out First 14nm FinFET Test Chip Targeting Samsung Process »

Cadence to Showcase Innovation for Prototyping and Early Software Development at embedded world 2013 »

Cadence Announces Availability of Industry's First Design IP and Verification IP for Ethernet-based Automotive Connectivity »

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 Cadence Events

"Early Prototyping and Software Development": Visit us in Hall 4/4-609
More information about our activities throughout the show here >>>

Technology on Tour: Club Formal
19 February, Cadence Bracknell, UK & 21 February 2013, Cadence Feldkirchen, Germany: Join the 3rd Club Formal user group meeting in Munich free of charge! Extend your formal verification expertise and learn more about general advances in the field.
Event details Bracknell »
Event details Munich »

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 Custom IC Design

Will LDE Stand Between You And Your Next Smart Device?
Electronicdesign.com, Tom Beckley, Cadence

Mobility is the key driver for today's consumer. Successful applications must provide technology integration, high bandwidth, and low power. Compared to 28 nm, 20 nm potentially provides upwards of 20% improved performance, 30% power savings, and a 50% area reduction that allows designers to place between 8 billion and 12 billion transistors on a single system-on-chip (SoC). 20-nm devices will fuel a new generation of smart phones, tablets, and other high-performance, low-power mobile devices. However, some technical challenges must be resolved before 20 nm is widely adopted.
Read full article »

Archived Webinar: Variation-Aware Analysis for Advanced Node Designs
By Richard Goering, Cadence

Why is variation such a big problem at 45nm and below, and what can custom/analog designers do to analyze and mitigate it? A new series of Cadence webinars on "variation-aware design" helps answer these questions. This blog post reviews the first webinar in the series, which was offered Nov. 7, 2012 and has since been archived.
Read blog and sign up for webinar »

An AMS Reference Flow for Power Management Designs
Semiwiki.com

A short summary of how TowerJazz and Cadence built and tested a Power Management IC Reference Flow version 2.0.
Read blog »

AMS IC Design at Rohde & Schwarz
Semiwiki.com

An interview with Frank Wiedmann, Rohde&Schwarz, about AMS design and methodologies used at Rohde&Schwarz.
Read interview »

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 Digital Implementation

ARM TechCon: Inside Story of a 14nm FinFET Tapeout
By Richard Goering, Cadence

The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using an ARM Cortex-M0 processor and IBM's FinFET process technology.
Read blog »

How to Close Timing with Hundreds of Multi-Mode/Multi-Corner Views
EE Journal.com, by Ruben Molina, Cadence

In the last decade we have seen the process of timing signoff become increasingly complex. Initial timing analyses at larger process nodes such as 180nm and 130nm were concerned mostly with operation at worst-case and best-case conditions. The distance between adjacent routing tracks was such that coupling capacitances were marginalized by ground and pin capacitance. Hence, engineers seldom looked at the potential issues associated with cross-coupling and noise effects. It was simply easier to add a small amount of margin than to analyze crosstalk.
Read full article »

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 Functional Verification

How to Verify Chips and Eliminate Bugs (cs348)
Enroll in Free Functional Hardware Verification Class now!!

When developing chips it is essential that they get verified thoroughly because it is very hard or impossible to fix them once they have been manufactured. In this class, you will learn how to program verification environments that verify chip functionality efficiently, as well as understand and leverage automation such as constrained random test generation and improve code reuse leveraging a standardized methodology.
All details here »

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 System Design and Verification

Hybrid Execution And Software-Driven Verification Will Emerge In 2013
ElectronicDesign. Com; by Frank Schirrmeister

Last year, I predicted that two things would happen in 2012 (see "The Next Level Of Design Entry-Will 2012 Bring Us There?"). First, I suggested that the hybrid, combined use of TLM simulation and the various ways to execute RTL (including hardware-assisted verification) would find further adoption. Second, I thought that more TLM modeling would be used in the FPGA space in which both main vendors were providing virtual prototyping solutions for their new FPGAs containing dual ARM subsystems. So, what happened?
Read full article »

The Agony Of Choice
System-Level Design Community.com; By Frank Schirrmeister

In my last post on "The Complexity of System Development and Verification" I outlined five main use models for verification at four levels of scope, enabled by seven execution engines. So how exactly do users choose between the different execution engines to run hardware and software together before the actual chip is available? It is far from trivial. The seven engines I identified are Software Development Kits, Virtual Prototypes, RTL Simulation, Acceleration, Emulation, FPGA Based Prototypes, and Development Kits that are based on the actual silicon samples once they are back from fabrication.
Read full article »

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 Low Power

imec - Leveraging the Cadence CPF-Driven Low-Power Solution for 4G Wireless Design

Antoine Dejonghe, Green Radio Program Manager at imec, highlights the use of the Cadence CPF-Driven Advanced Low-Power Solution that accelerates the company's next generation 4G
View video »

Building Energy-Efficient ICs from the Ground Up
SOC Central.com; by Pete Hardee

Power consumption has moved to the forefront of digital-IC development as component sizes shrink and insulating layers on gates become thinner. To enable today's advanced low-power techniques, the design flow must holistically address the architecture, design, verification, and implementation of low-power designs.
Read full article »

Perspective on Power: 2012 Survey Predicts 2013 as the Year of DVFS
By Pete Hardee, Cadence

In the last major surveys done almost two years ago (see the Perspective on Power blog from December 2010) we'd noticed that advanced low-power design techniques were starting to be applied outside of mobile (battery-operated) devices, and this trend has increased. 49% of the attendees surveyed worked on non-mobile end-applications. As in 2010, very nearly 100% were already using basic low-power techniques like clock gating and multi-Vt optimization. But the people using advanced techniques "currently" increased from 60% to 70%
Read blog »

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 Manufacturability Signoff

Cadence donates multi-patterned lithography technology
EETimes.com

Si2 announced that Cadence has donated extensions to the OpenAccess community which enable physical design tools to represent Multi-Patterned Technology (MPT). Conventional photolithography cannot accurately pattern the geometries required for the 20nm process node and below. Foundries have turned to various multi-patterning lithography techniques to address this issue. Shapes on the same layer manufactured with multi-patterned technology (MPT) are created through multiple exposures using multiple masks.
Read full article »

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 IP News

Cadence Announces Availability of Industry's First Design IP and Verification IP for Ethernet-based Automotive Connectivity

Cadence announced the immediate availability of the industry's first Automotive Ethernet Design IP and Verification IP (VIP) for the latest Automotive Ethernet Controllers. The standards-based Design IP and VIP support the latest Automotive Ethernet extensions as defined by the OPEN Alliance Special Interest Group (SIG). Together, both IP help speed today's newest automotive requirements to market, including improvements to in-vehicle safety, comfort, and infotainment as well as reductions in network complexity and cabling costs. Implementation of these new capabilities is made faster and easier by the Cadence® Media Access Controller (MAC) Design IP and VIP for Ethernet-based automotive connectivity.
Download datasheet here »

Forget design for reuse; the new mantra is 'build for change'
Newelectronics.co.uk;

In his keynote speech at last month's IPSoC conference - held in Grenoble's World Trade Centre - Cadence senior vp Martin Lund announced that IP reuse is an illusion. "The standard IP 'mall' concept is no longer working," he said. "Today, we need a factory approach to IP."
Read full article »

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 PCB

Customer Support Recommended - Pin Swapping in Allegro Design Entry CIS and PCB Editor - Blog by Naveen Konchada, Cadence

Placement and routing have always been an integral part of printed circuit board design. The productivity of the product is often (if not always) achieved best if the PCB has a proper placement of the components and effective routing to support the placement. With the increased complexity of the designs and smaller board sizes, routing of signals has become more challenging. Designers are always looking for ways to ease routing complexity and hence reduce the turnaround time.
Read blog »

What's Good About RF PCB and Layout? 16.6 Has Many New Enhancements!
Blog by Gerald "Jerry" Grzenia

The 16.6 Allegro RF PCB application has many new enhancements. I'll cover a few over the next several weeks. Here are some major layout related enhancements:

  • Snap Enhancements
  • Add Connect Enhancements
  • Modify Connectivity Enhancements
  • Add Component Enhancements
  • Scaled Copy Enhancements
  • Single Segment Connection
  • Route with Any Angle Bend
Read on for more details »

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 Cadence Academic Network

Cadence Academic Network at LinkedIn

In case you do not know, the Cadence Academic Network is providing its technical information via the LinkedIn® professional network. With a variety of subgroups for different technical fields, it is offering enhanced possibilities to receive tailored information.

You can find a lot of information about our groups, for example links to interesting webinars, videos, articles, technical demos, upcoming events, and a lot more. The groups are moderated by the lead institutions of the Cadence Academic Network, ensuring a constant flow of reviewed information relevant to academia.
Learn more about Cadence Academic Network at LinkedIn® »

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 Education Services

Developing the future and your technical skills is Education Services profession and passion.

If you are curious about our collection of latest top new class developments and plans for Sigrity tools but also self-paced online courses (iLS) for Allegro, please continue reading.

To check for a detailed agenda and further dates, please browse through our website www.cadence.com/training/eu.


new System SI Parallel Bus Analysis v12.0

This course covers the analysis of a DDR2 parallel bus interface to verify the operation of the bus using System SI Parallel Bus Analysis. You will define a DDR2 interface for a system and assign IBIS models to the components of the system. You will also learn how to add the power rail information to the IBIS models to include power distribution effects in the analysis. An S Parameter model will be extracted from a PCB database to be used in the simulation. You will generate a Bus Analysis report to verify that successful operation of the bus interface.

new System SI Serial Link Analysis v12.0

The course uses System SI Serial Link Analysis to analyze high-speed channels and view the results in a variety of different formats. You will define the components of the channel based on pre-defined templates and use IBIS AMI models for both transmitters and receivers components. You will modify the parameters of the AMI modes to view the effects of the output eye opening. The Sweep Manager is used to sweep multiple parameters simultaneously and manage a large number of simulations. You will also use the Block Sensitivity analyzer to compare the sensitivity of the channel to noise and jitter from each component in the system. You will also extract S-parameter models for the different components in the system.

On demand
  • Allegro Sigrity SI Base
  • Allegro Sigrity SI Base plus Power-Aware SI Analysis
  • Allegro Sigrity SI Base and/or Allegro Sigrity PI Base plus Package Assessment and Model Extraction
  • Allegro Sigrity SI Base plus the System-Level Serial Link Analysis

INTERNET LEARNING SERIES (ILS) FOR ALLEGRO TOOLS

Did you know we offer over 50 courses in Internet Learning Series (iLS) formatting?
Our internet based courses include dynamic course content, downloadable labs, instructor notes and bulletin boards. Available within 3 days, 24/7.

Our offering for Allegro courses in 16.5/16.6 includes, but is not limited to:


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