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February 2012 Issue
 In this issue
In the News
Cadence Events
Industry Events
System Design and Verification
Logic Design
Functional Verification
Custom IC Design
Manufacturability Signoff
Digital Implementation
PCB and SiP design, IC packaging
Cadence Academic Network
Education Services
 Quick links
Cadence blogs
Events
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Welcome to the first edition of eEuronews in 2012!

We are starting into the new year with a range of Cadence and public industry events. In the event section below, you will find a list of our activities at embedded world in Nuremberg and at DATE in Dresden, as well as all the details on how to register to the latest EDA360 Technology on Tour seminars taking place in Germany and Israel.

For everyone who is interested in an authoritative source of information about business and technology trends in semiconductor memory and storage, we want to let you know that the very popular Denali Memory Report is back. The report will cover memory market news, market trends, products and product strategies of memory vendors, alliances and industry consortia. Don't miss it.

To all who have submitted their paper abstract for CDNLive! EMEA 2012 on or before December 14, 2011, I am happy to announce that Johannes Brücker from Renesas in Duesseldorf has won the iNano. Congratulations!

We are currently in the process of preparing the agenda for the CDNLive! EMEA conference and the registration site will be opening soon! Stay tuned.

Best regards,

Wolfgang Stronski
Marketing Director EMEA, Cadence

P.S. Check out the new training schedule offered by Cadence and Esperan

 News
Cadence Reports Fourth Quarter and Fiscal Year 2011 Financial Results »

Cadence Expands Proven NAND Flash Design IP Offering with ONFI 3 PHY and Controller »

Cadence Collaborates with Samsung Foundry to Deliver Design-for-Manufacturing Solution for 32-, 28- and 20-Nanometer Chip Design »

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 Cadence Events
EDA360 Technology on Tour: Silicon Realization - Club Formal
16. Feb 2012, Cadence Office, Feldkirchen, Germany
Join the 2nd Club Formal user group meeting in Feldkirchen! Extend your formal verification expertise and learn more about general advances in the field.

Details »

EDA360 Silicon Realization Technology on Tour - Logic Design Event
27. Feb 2012, Cadence Office, Herzelia, Israel
Learn, Share Ideas and Network with Cadence Logic Design Users and R&D Experts.

Details »

Webinars: Free, On-Demand "Tech on Tour" - Digital, Custom/Analog, and PCB

For some time Cadence has offered EDA360 "Technology on Tour" presentations in various cities. Now Cadence is offering on-line Technology on Tour presentations at your desktop, any time, for free. These technical presentations and demos show how to solve common design challenges, and provide the latest information about Cadence custom/analog, digital, and PCB design technologies.

Most of the presentations are in the 30 minute to one hour range, although a few are shorter. Many include both slide presentations and demos. The sessions are available to Cadence Community members (quick, free registration if you don't have one yet).

Details »

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 Industry Events
embedded world, Feb 28 - March 1, 2012: Cadence on Xilinx Booth, Hall 1/1-205

Stop by the Xilinx booth and see Cadence's virtual platform of the Xilinx Zynq-7000 Extensible Processing Platform (EPP). The Cadence Virtual Platform for Xilinx Zynq-7000 Extensible Processing Platform (EPP) models a Xilinx Target Reference Design comprised of the Zynq-7000 EPP's processing system, including dual ARM A9 core processor, all processing system peripherals, and on-board devices. Embedded World 2012

The Cadence Virtual Platform Creator allows developers to extend the off-the-shelf virtual platform with custom peripherals that would be instantiated within the programmable fabric, or on the board. This extensibility enables both pre-firmware and pre-RTL software development, offering improved parallelism and reduced project schedule. Don't miss the opportunity to take a closer look at this virtual platform solution for faster embedded software development.

Thursday, March 1st, from 15.30-16.00
Test and Verification, Session 19


Power Management Test and Verification for Hardware/Software Systems
Speaker: Markus Winterholer, Cadence

The presentation will discuss low power test and verification challenges and will demonstrate a complete metric driven solution to ensure low power design quality.



DATE 12 Cadence at DATE, March 12-16, 2012, Dresden, Germany Cadence has a station on the GLOBALFOUNDRIES Booth # 49

Selection of Cadence's activities:

Monday, March 12, 2012
F2 Tutorial: Design methodology and techniques in production low-power SOC designs.
Time: 1430 - 1800     Location / Room: Konferenz 1

Tuesday, March 13, 2012
Special Session - HOT TOPIC: EDA Solutions to New-Defect Detection in Advanced Process Technologies
Time: 1130 - 1300     Location / Room: Konferenz 5

Wednesday, March 14, 2012
Special Session - Panel: Accelerators and emulators: Can they become the platform of choice for hardware verification?
Time: 0830 - 1000     Location / Room: Konferenz 6

Special Day E-MOBILITY - Panel: Role of EDA in the Development of Electric Vehicles - Time: 1100 - 1230 Location / Room: Saal 5

Special Session - HOT TOPIC: Virtual Platforms: Breaking New Grounds.
Time: 1430 - 1600     Location / Room: Konferenz 6

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 System Design and Verification
Cadence Palladium XP Verification Computing Platform Speeds Deployment of Panasonic System-on-Chip for Digital Consumer Products

Panasonic Corporation has deployed the Cadence Palladium XP Verification Computing Platform, part of the Cadence System Development Suite, to speed the design of System-on-Chips (SoC) for next-generation digital consumer products such as Smart TVs and video recorders. Palladium XP unifies simulation, acceleration and emulation capabilities in a single environment enabling hardware-software system verification. Consequently, customers like Panasonic can rapidly verify their complex SoC designs for cutting-edge consumer products.

Using Palladium XP, Panasonic was able to test complex functions and verify hardware-software integration. Specifically, the company was able to connect a validation environment to the Palladium XP system, providing graphic validation capabilities of both hardware and software.

Read more »

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 Logic Design
User View: "Multi-Mode" Synthesis Approach Includes Power Optimization
Blog by Richard Goering, Cadence

Logic synthesis is an indispensible IC design tool, but its value has a lot to do with how it's used. At a recent Synthesis Community Event at Cadence Dec. 8, Laszlo Borbely-Bartis, staff design engineer at Micron, described a concurrent multi-mode and low-power optimization synthesis flow using the Common Power Format (CPF). The new flow provides many advantages compared to the traditional bottom-up, single-mode synthesis approach.

Read More »

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 Functional Verification
Cadence Publishes Definitive Book on Advanced Verification for Today's ICs

Advanced Verification Topics book cover Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that it has published a new book to aid verification engineers. "Advanced Verification Topics" describes in great detail the latest techniques and methodologies for verifying today's most complex IP and systems on chips (SoCs). Penned by eight Cadence verification experts, "Advanced Verification Topics" builds on the prior Cadence® book, "A Practical Guide to Adopting the Universal Verification Methodology (UVM)." The new book delves into such topics as metric-driven verification of digital and mixed-signal designs, low-power verification using the UVM, multi-language UVM, and acceleration for the UVM.
"With the march toward greater design complexity showing no sign of abating, comprehensive verification is essential for a company to achieve its profitability goals," said Hao Fang, IP design manager at LSI. "'Advanced Verification Topics' will be an important reference book for teams responsible for verifying complex mixed-signal IP and SoCs that utilize low-power, verification IP (VIP), transaction-level models (TLM), acceleration, and similar techniques to reduce risk while getting end products into working silicon faster."

The 229-page "Advanced Verification Topics" is available now at Amazon.com and Lulu.com

Read More »

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 Custom IC Design
Blog: Things You Didn't Know About Virtuoso: We've Got You Cornered
by Stacy Whiteman, Cadence

One of the big buzzwords around the EDA world these days is "variation." Don't you just love buzzwords? Take a perfectly normal, slightly ambiguous word, capitalize it, add another slightly ambiguous hyphenated suffix, and suddenly you've just solved a new problem for your customers. "Interface-driven'' "user-centric'', "platform-based" and "variation-aware."

Read Blog »

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 Manufacturability Signoff
Blog: SPIE Papers Showcase DFM and Lithography R&D

Ten Cadence papers planned for the upcoming SPIE Advanced Lithography conference, set for Feb. 12-16 in San Jose, California, demonstrate recent R&D developments in both "design side" design for manufacturing (DFM) and the computational lithography that takes place during the manufacturing phase. The papers will be given Feb. 14-16 and are all co-authored with customers or partners.

Read Blog »

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 Digital Implementation
Technical article: Clock-Concurrent Optimization Reshapes IC Physical Design Flow
Chipdesignmag.com, Nov 2011- by Paul Cunningham and Steve Wilcox, Cadence

No modern, synchronous integrated circuit (IC) can function without a clock network. Clock-tree synthesis (CTS), which distributes clock signals to data registers, is a critical step in the IC physical design flow. But the traditional approach to CTS, which is based on minimizing clock skew and is separate from logic optimization, is breaking down for advanced-node, high-speed designs. The problem is that today's chip designers are facing a growing "timing gap" between the ideal clocks assumed pre-CTS and the more accurate propagated clocks, which emerge after CTS. This timing gap is driven by factors like clock gating for low power, on-chip variation, and design complexity.

Read more »

Blog: Three Die Stack - A Big Step "Up" for 3D-ICs with TSVs

A major advancement in 3D-IC through-silicon via (TSV) design was unveiled as representatives of CEA-LETI and ST-Ericsson describe the development of a three-die stack with wide I/O memory and logic. This tapeout is the result of collaboration between these two organizations and Cadence, which provided the design tools and the wide I/O controller IP for the project.

Read blog »

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 PCB and SiP design, IC packaging
What's Good About PCB SI Signal Integrity Application Mode? It's in the 16.5 Release!
By Gerald "Jerry" Grzenia

In release 16.0, the concept of Application Modes was introduced. These application modes are used to set up the tool for specific tasks. The existing applications are General Edit, Etch Edit, and Placement. In 16.5, the Signal Integrity (SI) application mode has been added to be used for high-speed related tasks.

An Application Mode is a "super command" telling Allegro the general function area the user will be working in, and includes the following related functionality:

• Highlighting objects on hover
• Context sensitive RMB menus
• Auto-execution of default commands on double-click or drag of an object
• A limited Find Filter

Read blog »

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 Cadence Academic Network
Cadence Academic Network @ LinkedIn

In the beginning of 2011, the team of Cadence Academic Network started to use LinkedIn as a medium to provide technical updates to the Network. The following link will give you more information about how to engage with our groups and how to receive tailored information and notification about upcoming events.

Click here »

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 Education Services
SPICE Seminar - Learn from the author of "The SPICE book"
Dr. Andrei Vladimirescu will be hosting The SPICE Seminar, 20th-23rd March 2012

The Spice Book cover The purpose of the course is to help circuit designers better understand semiconductor device modeling, with emphasis on Deep-Submicron (DSM) technology and the operation of a SPICE circuit simulator. The course also addresses the different levels of modeling, structural and behavioral, simulation controls available to the user and new types of analysis such as steady-state, particularly suited for RF design. Participants will have an opportunity to experiment with the various concepts presented in the course on workstations.

Learn more »

new Analog-on-Top Mixed Signal Implementation

This newly developed training course targets experienced Analog Layouters and CAD Engineers who aim to implement designs in a Mixed Signal Environment. Within this 3 day training you gain experience in the area of Mixed Signal Implementation.

Please check here for a detailed agenda.

new In our training portfolio

SKILL Language Programming vIC 6.1.5
SystemVerilog Advanced Verification Using UVM v1.1
Encounter RTL Compiler v11.15

New Schedule 2012 Released

Have a look at cadence.com/training/eu and esperan.com to find our dates planned for January-June 2012. Our Education Services team is happy to assist in finding the right training for you, so feel free to contact us.

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©2011 Cadence Design Systems, Inc. All rights reserved.

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